SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
The CTL2.FIFOTRIGSEL register is used to select the trigger source for loading data from FIFO into internal DAC data register. There are three triggers sources:
For the hardware trigger source, the DAC module can subscribe to the event through the event fabric. Setting CTR2.FIFOTRIGSEL as 1 is to subscribe to the event on FSUB_0.
When the sample time generator is used, the MFPCLK is used for trigger generation and for transferring the data from FIFO into internal DAC data register. In this scenario, the DAC sampling rate is predictable and has no connection with ULPCLK.
When the sample time generator is not used, the ULPCLK is used for transferring the data from FIFO into internal DAC data register upon the external event trigger. For a predictable DAC sampling rate, the application software must manage ULPCLK frequency to be deterministic. The sampling rate is affected if there is any change in ULPCLK frequency during DAC operation in this scenario.
Whenever the selected trigger source is asserted, the data in FIFO pointed by the read pointer is read and loaded into the internal DAC data register for conversion.