SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

10.3 ADC12 Registers

Table 10-10 lists the memory-mapped registers for the ADC12 registers. All register offset addresses not listed in Table 10-10 should be considered as reserved locations and the register contents should not be modified.

Table 10-10 ADC12 Registers
OffsetAcronymRegister NameGroupSection
400hFSUB_0Subscriber Configuration Register.Go
444hFPUB_1Publisher Configuration Register.Go
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
808hCLKCFGADC clock configuration RegisterGo
814hSTATStatus RegisterGo
1020hIIDXInterrupt indexCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1050hIIDXInterrupt indexGEN_EVENTGo
1058hIMASKInterrupt maskGEN_EVENTGo
1060hRISRaw interrupt statusGEN_EVENTGo
1068hMISMasked interrupt statusGEN_EVENTGo
1070hISETInterrupt setGEN_EVENTGo
1078hICLRInterrupt clearGEN_EVENTGo
1080hIIDXInterrupt indexDMA_TRIGGo
1088hIMASKInterrupt mask extensionDMA_TRIGGo
1090hRISRaw interrupt status extensionDMA_TRIGGo
1098hMISMasked interrupt status extensionDMA_TRIGGo
10A0hISETInterrupt set extensionDMA_TRIGGo
10A8hICLRInterrupt clear extensionDMA_TRIGGo
10E0hEVT_MODEEvent ModeGo
10FChDESCModule DescriptionGo
1100hCTL0Control Register 0Go
1104hCTL1Control Register 1Go
1108hCTL2Control Register 2Go
110ChCTL3Control Register 3Go
1110hCLKFREQSample Clock Frequency Range RegisterGo
1114hSCOMP0Sample Time Compare 0 RegisterGo
1118hSCOMP1Sample Time Compare 1 RegisterGo
111ChREFCFGReference Buffer Configuration RegisterGo
1148hWCLOWWindow Comparator Low Threshold RegisterGo
1150hWCHIGHWindow Comparator High Threshold RegisterGo
1160hFIFODATAFIFO Data RegisterGo
1170hASCRESASC Result RegisterGo
1180h + formulaMEMCTL[y]Conversion Memory Control RegisterGo
1280h + formulaMEMRES[y]Memory Result RegisterGo
1340hSTATUSStatus RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 10-11 shows the codes that are used for access types in this section.

Table 10-11 ADC12 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

10.3.1 FSUB_0 (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 10-5 and described in Table 10-12.

Return to the Summary Table.

Subscriber port

Figure 10-5 FSUB_0
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 10-12 FSUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 255.

10.3.2 FPUB_1 (Offset = 444h) [Reset = 00000000h]

FPUB_1 is shown in Figure 10-6 and described in Table 10-13.

Return to the Summary Table.

Publisher port

Figure 10-6 FPUB_1
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDCHANID
R/W-0hR/W-0h
Table 10-13 FPUB_1 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 255.

10.3.3 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 10-7 and described in Table 10-14.

Return to the Summary Table.

Register to control the power state

Figure 10-7 PWREN
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/WK-0h
Table 10-14 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLER/WK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

10.3.4 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 10-8 and described in Table 10-15.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 10-8 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 10-15 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

10.3.5 CLKCFG (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Figure 10-9 and described in Table 10-16.

Return to the Summary Table.

ADC clock configuration

Figure 10-9 CLKCFG
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDCCONSTOPCCONRUNRESERVEDSAMPCLK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-16 CLKCFG Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
A9h = KEY to allow write access to this register
23-6RESERVEDR/W0h
5CCONSTOPR/W0hCCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source.
0h = ADC conversion clock source is not kept continuously on during STOP mode.
1h = ADC conversion clock source kept continuously on during STOP mode.
4CCONRUNR/W0hCCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source.
0h = ADC conversion clock source is not kept continuously on during RUN mode.
1h = ADC conversion clock source kept continuously on during RUN mode.
3-2RESERVEDR/W0h
1-0SAMPCLKR/W0hADC sample clock source selection.
0h = ULPCLK is the source of ADC sample clock.
1h = SYSOSC is the source of ADC sample clock.
2h = HFCLK clock is the source of ADC sample clock.
Note : HFCLK may not be available on all the devices.

10.3.6 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 10-10 and described in Table 10-17.

Return to the Summary Table.

peripheral enable and reset status

Figure 10-10 STAT
3130292827262524
RESERVED
R-
2322212019181716
RESERVEDRESETSTKY
R-R-0h
15141312111098
RESERVED
R-
76543210
RESERVED
R-
Table 10-17 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

10.3.7 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 10-11 and described in Table 10-18.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, … 231 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 10-11 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 10-18 IIDX Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9-0STATR0hInterrupt index status
00h = No bit is set means there is no pending interrupt request
01h = MEMRESx overflow interrupt
02h = Sequence Conversion time overflow interrupt
03h = High threshold compare interrupt
04h = Low threshold compare interrupt
05h = Primary Sequence In range comparator interrupt
6h = DMA done interrupt, generated on DMA transfer completion,
07h = MEMRESx underflow interrupt
9h = MEMRES0 data loaded interrupt
Ah = MEMRES1 data loaded interrupt
Bh = MEMRES2 data loaded interrupt
Ch = MEMRES3 data loaded interrupt
Dh = MEMRES4 data loaded interrupt
Eh = MEMRES5 data loaded interrupt
Fh = MEMRES6 data loaded interrupt
10h = MEMRES7 data loaded interrupt
11h = MEMRES8 data loaded interrupt
12h = MEMRES9 data loaded interrupt
13h = MEMRES10 data loaded interrupt
14h = MEMRES11 data loaded interrupt
15h = MEMRES12 data loaded interrupt
16h = MEMRES13 data loaded interrupt
17h = MEMRES14 data loaded interrupt
18h = MEMRES15 data loaded interrupt
19h = MEMRES16 data loaded interrupt
1Ah = MEMRES17 data loaded interrupt
1Bh = MEMRES18 data loaded interrupt
1Ch = MEMRES19 data loaded interrupt
1Dh = MEMRES20 data loaded interrupt
1Eh = MEMRES21 data loaded interrupt
1Fh = MEMRES22 data loaded interrupt
20h = MEMRES23 data loaded interrupt

10.3.8 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 10-12 and described in Table 10-19.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 10-12 IMASK
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-19 IMASK Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23R/W0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22R/W0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21R/W0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20R/W0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19R/W0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18R/W0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17R/W0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16R/W0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15R/W0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14R/W0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13R/W0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12R/W0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11R/W0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10R/W0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9R/W0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8R/W0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7R/W0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6R/W0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5R/W0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4R/W0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER/W0hMask for ASC done raw interrupt flag
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER/W0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

10.3.9 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 10-13 and described in Table 10-20.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 10-13 RIS
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 10-20 RIS Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23R0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22R0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21R0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20R0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19R0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18R0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17R0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16R0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15R0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14R0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13R0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12R0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11R0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10R0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9R0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8R0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7R0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6R0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5R0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4R0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3R0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hRaw interrupt flag for ASC done
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR0hRaw interrupt flag for sequence conversion trigger overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

10.3.10 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 10-14 and described in Table 10-21.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 10-14 MIS
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 10-21 MIS Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23R0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22R0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21R0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20R0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19R0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18R0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17R0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16R0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15R0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14R0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13R0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12R0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11R0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10R0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9R0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8R0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7R0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6R0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5R0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4R0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3R0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER0hMasked interrupt status for ASC done
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

10.3.11 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 10-15 and described in Table 10-22.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 10-15 ISET
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 10-22 ISET Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23W0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22W0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21W0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20W0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19W0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18W0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17W0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16W0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15W0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14W0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13W0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12W0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11W0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10W0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9W0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8W0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7W0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6W0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5W0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4W0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONEW0hSet ASC done flag in RIS
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGW0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONEW0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGW0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGW0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGW0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGW0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGW0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

10.3.12 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 10-16 and described in Table 10-23.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 10-16 ICLR
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
ASCDONEUVIFGDMADONEINIFGLOWIFGHIGHIFGTOVIFGOVIFG
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 10-23 ICLR Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23W0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22W0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21W0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20W0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19W0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18W0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17W0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16W0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15W0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14W0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13W0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12W0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11W0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10W0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9W0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8W0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7W0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6W0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5W0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4W0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONEW0hClear ASC done flag in RIS
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGW0hRaw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONEW0hRaw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGW0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGW0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGW0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGW0hRaw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGW0hRaw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.

10.3.13 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 10-17 and described in Table 10-24.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, … 231 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 10-17 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 10-24 IIDX Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9-0STATR0hInterrupt index status
00h = No bit is set means there is no pending interrupt request
03h = High threshold compare interrupt
04h = Low threshold compare interrupt
05h = Primary Sequence In range comparator interrupt
9h = MEMRES0 data loaded interrupt

10.3.14 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 10-18 and described in Table 10-25.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 10-18 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDMEMRESIFG0
R/W-0hR/W-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-25 IMASK Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR/W0h
4INIFGR/W0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR/W0h

10.3.15 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 10-19 and described in Table 10-26.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 10-19 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR-0hR-0hR-0hR-0h
Table 10-26 RIS Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

10.3.16 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 10-20 and described in Table 10-27.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 10-20 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMEMRESIFG0
R-0hR-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
R-0hR-0hR-0hR-0hR-0h
Table 10-27 MIS Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0h
4INIFGR0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0h

10.3.17 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 10-21 and described in Table 10-28.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 10-21 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDMEMRESIFG0
W-0hW-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
W-0hW-0hW-0hW-0hW-0h
Table 10-28 ISET Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDW0h
8MEMRESIFG0W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDW0h
4INIFGW0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGW0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGW0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDW0h

10.3.18 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 10-22 and described in Table 10-29.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 10-22 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVEDMEMRESIFG0
W-0hW-0h
76543210
RESERVEDINIFGLOWIFGHIGHIFGRESERVED
W-0hW-0hW-0hW-0hW-0h
Table 10-29 ICLR Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDW0h
8MEMRESIFG0W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDW0h
4INIFGW0hMask INIFG in MIS_EX register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGW0hRaw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGW0hRaw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDW0h

10.3.19 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 10-23 and described in Table 10-30.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. 0x0 means no event pending. Interrupt 1 is the highest priority, 2 next highest, 4, 8, … 231 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.

On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 10-23 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 10-30 IIDX Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9-0STATR0hInterrupt index status
00h = No bit is set means there is no pending interrupt request
9h = MEMRES0 data loaded interrupt
Ah = MEMRES1 data loaded interrupt
Bh = MEMRES2 data loaded interrupt
Ch = MEMRES3 data loaded interrupt
Dh = MEMRES4 data loaded interrupt
Eh = MEMRES5 data loaded interrupt
Fh = MEMRES6 data loaded interrupt
10h = MEMRES7 data loaded interrupt
11h = MEMRES8 data loaded interrupt
12h = MEMRES9 data loaded interrupt
13h = MEMRES10 data loaded interrupt
14h = MEMRES11 data loaded interrupt
15h = MEMRES12 data loaded interrupt
16h = MEMRES13 data loaded interrupt
17h = MEMRES14 data loaded interrupt
18h = MEMRES15 data loaded interrupt
19h = MEMRES16 data loaded interrupt
1Ah = MEMRES17 data loaded interrupt
1Bh = MEMRES18 data loaded interrupt
1Ch = MEMRES19 data loaded interrupt
1Dh = MEMRES20 data loaded interrupt
1Eh = MEMRES21 data loaded interrupt
1Fh = MEMRES22 data loaded interrupt
20h = MEMRES23 data loaded interrupt

10.3.20 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 10-24 and described in Table 10-31.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 10-24 IMASK
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVED
R/W-0h
Table 10-31 IMASK Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23R/W0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22R/W0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21R/W0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20R/W0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19R/W0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18R/W0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17R/W0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16R/W0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15R/W0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14R/W0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13R/W0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12R/W0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11R/W0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10R/W0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9R/W0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8R/W0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7R/W0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6R/W0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5R/W0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4R/W0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR/W0h

10.3.21 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 10-25 and described in Table 10-32.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 10-25 RIS
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 10-32 RIS Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23R0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22R0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21R0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20R0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19R0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18R0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17R0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16R0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15R0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14R0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13R0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12R0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11R0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10R0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9R0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8R0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7R0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6R0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5R0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4R0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3R0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

10.3.22 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 10-26 and described in Table 10-33.

Return to the Summary Table.

Extension of Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 10-26 MIS
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVED
R-0h
Table 10-33 MIS Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23R0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22R0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21R0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20R0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19R0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18R0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17R0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16R0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15R0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14R0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13R0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12R0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11R0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10R0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9R0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8R0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7R0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6R0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5R0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4R0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3R0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0h

10.3.23 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 10-27 and described in Table 10-34.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 10-27 ISET
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVED
W-0h
Table 10-34 ISET Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23W0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22W0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21W0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20W0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19W0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18W0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17W0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16W0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15W0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14W0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13W0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12W0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11W0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10W0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9W0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8W0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7W0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6W0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5W0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4W0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDW0h

10.3.24 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 10-28 and described in Table 10-35.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 10-28 ICLR
3130292827262524
MEMRESIFG23MEMRESIFG22MEMRESIFG21MEMRESIFG20MEMRESIFG19MEMRESIFG18MEMRESIFG17MEMRESIFG16
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
2322212019181716
MEMRESIFG15MEMRESIFG14MEMRESIFG13MEMRESIFG12MEMRESIFG11MEMRESIFG10MEMRESIFG9MEMRESIFG8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
MEMRESIFG7MEMRESIFG6MEMRESIFG5MEMRESIFG4MEMRESIFG3MEMRESIFG2MEMRESIFG1MEMRESIFG0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
RESERVED
W-0h
Table 10-35 ICLR Field Descriptions
BitFieldTypeResetDescription
31MEMRESIFG23W0hRaw interrupt status for MEMRES23.
This bit is set to 1 when MEMRES23 is loaded with a new
conversion result.
Reading MEMRES23 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
30MEMRESIFG22W0hRaw interrupt status for MEMRES22.
This bit is set to 1 when MEMRES22 is loaded with a new
conversion result.
Reading MEMRES22 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
29MEMRESIFG21W0hRaw interrupt status for MEMRES21.
This bit is set to 1 when MEMRES21 is loaded with a new
conversion result.
Reading MEMRES21 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
28MEMRESIFG20W0hRaw interrupt status for MEMRES20.
This bit is set to 1 when MEMRES20 is loaded with a new
conversion result.
Reading MEMRES20 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
27MEMRESIFG19W0hRaw interrupt status for MEMRES19.
This bit is set to 1 when MEMRES19 is loaded with a new
conversion result.
Reading MEMRES19 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
26MEMRESIFG18W0hRaw interrupt status for MEMRES18.
This bit is set to 1 when MEMRES18 is loaded with a new
conversion result.
Reading MEMRES18 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
25MEMRESIFG17W0hRaw interrupt status for MEMRES17.
This bit is set to 1 when MEMRES17 is loaded with a new
conversion result.
Reading MEMRES17 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
24MEMRESIFG16W0hRaw interrupt status for MEMRES16.
This bit is set to 1 when MEMRES16 is loaded with a new
conversion result.
Reading MEMRES16 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
23MEMRESIFG15W0hRaw interrupt status for MEMRES15.
This bit is set to 1 when MEMRES15 is loaded with a new
conversion result.
Reading MEMRES15 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
22MEMRESIFG14W0hRaw interrupt status for MEMRES14.
This bit is set to 1 when MEMRES14 is loaded with a new
conversion result.
Reading MEMRES14 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
21MEMRESIFG13W0hRaw interrupt status for MEMRES13.
This bit is set to 1 when MEMRES13 is loaded with a new
conversion result.
Reading MEMRES13 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
20MEMRESIFG12W0hRaw interrupt status for MEMRES12.
This bit is set to 1 when MEMRES12 is loaded with a new
conversion result.
Reading MEMRES12 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
19MEMRESIFG11W0hRaw interrupt status for MEMRES11.
This bit is set to 1 when MEMRES11 is loaded with a new
conversion result.
Reading MEMRES11 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
18MEMRESIFG10W0hRaw interrupt status for MEMRES10.
This bit is set to 1 when MEMRES10 is loaded with a new
conversion result.
Reading MEMRES10 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
17MEMRESIFG9W0hRaw interrupt status for MEMRES9.
This bit is set to 1 when MEMRES9 is loaded with a new
conversion result.
Reading MEMRES9 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
16MEMRESIFG8W0hRaw interrupt status for MEMRES8.
This bit is set to 1 when MEMRES8 is loaded with a new
conversion result.
Reading MEMRES8 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
15MEMRESIFG7W0hRaw interrupt status for MEMRES7.
This bit is set to 1 when MEMRES7 is loaded with a new
conversion result.
Reading MEMRES7 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
14MEMRESIFG6W0hRaw interrupt status for MEMRES6.
This bit is set to 1 when MEMRES6 is loaded with a new
conversion result.
Reading MEMRES6 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
13MEMRESIFG5W0hRaw interrupt status for MEMRES5.
This bit is set to 1 when MEMRES5 is loaded with a new
conversion result.
Reading MEMRES5 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
12MEMRESIFG4W0hRaw interrupt status for MEMRES4.
This bit is set to 1 when MEMRES4 is loaded with a new
conversion result.
Reading MEMRES4 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
11MEMRESIFG3W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDW0h

10.3.25 EVT_MODE (Offset = 10E0h) [Reset = 00000009h]

EVT_MODE is shown in Figure 10-29 and described in Table 10-36.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 10-29 EVT_MODE
3130292827262524
RESERVED
R-
2322212019181716
RESERVED
R-
15141312111098
RESERVED
R-
76543210
RESERVEDEVT1_CFGINT0_CFG
R-R-2hR-1h
Table 10-36 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-2EVT1_CFGR2hEvent line mode select for event corresponding to GEN_EVENT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR1hEvent line mode select for event corresponding to CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

10.3.26 DESC (Offset = 10FCh) [Reset = 26110010h]

DESC is shown in Figure 10-30 and described in Table 10-37.

Return to the Summary Table.

This register identifies the peripheral and its exact version.

Figure 10-30 DESC
31302928272625242322212019181716
MODULEID
R-2611h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-0hR-0hR-1hR-0h
Table 10-37 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR2611hModule identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR0hFeature Set for the module *instance*
0h = Smallest value
Fh = Highest possible value
11-8INSTNUMR0hInstance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
7-4MAJREVR1hMajor rev of the IP
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor rev of the IP
0h = Smallest value
Fh = Highest possible value

10.3.27 CTL0 (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Figure 10-31 and described in Table 10-38.

Return to the Summary Table.

Control Register 0

Figure 10-31 CTL0
3130292827262524
RESERVEDSCLKDIV
R/W-0hR/W-0h
2322212019181716
RESERVEDPWRDN
R/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENC
R/W-0hRH/W-0h
Table 10-38 CTL0 Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR/W0h
26-24SCLKDIVR/W0hSample clock divider
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 4
3h = Divide clock source by 8
4h = Divide clock source by 16
5h = Divide clock source by 24
6h = Divide clock source by 32
7h = Divide clock source by 48
23-17RESERVEDR/W0h
16PWRDNR/W0hPower down policy
0h = ADC is powered down on completion of a conversion if there is no pending trigger
1h = ADC remains powered on as long as it is enabled through software.
15-1RESERVEDR/W0h
0ENCRH/W0hEnable conversion
0h = Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
1h = Conversion enabled. ADC sequencer waits for valid trigger (software or hardware).

10.3.28 CTL1 (Offset = 1104h) [Reset = 00000000h]

CTL1 is shown in Figure 10-32 and described in Table 10-39.

Return to the Summary Table.

Control Register 1

Figure 10-32 CTL1
3130292827262524
RESERVEDAVGDRESERVEDAVGN
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDSAMPMODERESERVEDCONSEQ
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDSC
R/W-0hRH/W-0h
76543210
RESERVEDTRIGSRC
R/W-0hR/W-0h
Table 10-39 CTL1 Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0h
30-28AVGDR/W0hHardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated.
0h (R/W) = No shift
1h (R/W) = 1 bit shift
2h (R/W) = 2 bit shift
3h (R/W) = 3 bit shift
4h (R/W) = 4 bit shift
5h (R/W) = 5 bit shift
6h (R/W) = 6 bit shift
7h (R/W) = 7 bit shift
27RESERVEDR/W0h
26-24AVGNR/W0hHardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx.
0h (R/W) = Disables averager
1h (R/W) = Averages 2 conversions before storing in MEMRESx register
2h (R/W) = Averages 4 conversions before storing in MEMRESx register
3h (R/W) = Averages 8 conversions before storing in MEMRESx register
4h (R/W) = Averages 16 conversions before storing in MEMRESx register
5h (R/W) = Averages 32 conversions before storing in MEMRESx register
6h (R/W) = Averages 64 conversions before storing in MEMRESx register
7h (R/W) = Averages 128 conversions before storing in MEMRESx register
23-21RESERVEDR/W0h
20SAMPMODER/W0hSample mode. This bit selects the source of the sampling signal.
MANUAL option is not valid when TRIGSRC is selected as hardware event trigger.
0h = Sample timer high phase is used as sample signal
1h = Software trigger is used as sample signal
19-18RESERVEDR/W0h
17-16CONSEQR/W0hConversion sequence mode

0h = ADC channel in MEMCTLx pointed by STARTADD will be converted once

1h = ADC channel sequence pointed by STARTADD and ENDADD will be converted once
2h = ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly

3h = ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
15-9RESERVEDR/W0h
8SCRH/W0hStart of conversion

0h = When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start.
When SAMPMODE is set to AUTO, writing 0 has no effect.
1h = When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set.
When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
7-1RESERVEDR/W0h
0TRIGSRCR/W0hSample trigger source
0h = Software trigger


1h = Hardware event trigger

10.3.29 CTL2 (Offset = 1108h) [Reset = 00000000h]

CTL2 is shown in Figure 10-33 and described in Table 10-40.

Return to the Summary Table.

Control Register 2

Figure 10-33 CTL2
3130292827262524
RESERVEDENDADD
R/W-0hR/W-0h
2322212019181716
RESERVEDSTARTADD
R/W-0hR/W-0h
15141312111098
SAMPCNTFIFOENRESERVEDDMAEN
R/W-0hR/W-0hR/W-0hRH/W-0h
76543210
RESERVEDRESDF
R/W-0hR/W-0hR/W-0h
Table 10-40 CTL2 Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28-24ENDADDR/W0hSequence end address. These bits select which MEMCTLx is the last one for the sequence mode.
The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
00h = MEMCTL0 is selected as end address of sequence.
01h = MEMCTL1 is selected as end address of sequence.
02h = MEMCTL2 is selected as end address of sequence.
03h = MEMCTL3 is selected as end address of sequence.
04h = MEMCTL4 is selected as end address of sequence.
05h = MEMCTL5 is selected as end address of sequence.
06h = MEMCTL6 is selected as end address of sequence.
07h = MEMCTL7 is selected as end address of sequence.
08h = MEMCTL8 is selected as end address of sequence.
09h = MEMCTL9 is selected as end address of sequence.
0Ah = MEMCTL10 is selected as end address of sequence.
0Bh = MEMCTL11 is selected as end address of sequence.
0Ch = MEMCTL12 is selected as end address of sequence.
0Dh = MEMCTL13 is selected as end address of sequence.
0Eh = MEMCTL14 is selected as end address of sequence.
0Fh = MEMCTL15 is selected as end address of sequence.
10h = MEMCTL16 is selected as end address of sequence.
11h = MEMCTL17 is selected as end address of sequence.
12h = MEMCTL18 is selected as end address of sequence.
13h = MEMCTL19 is selected as end address of sequence.
14h = MEMCTL20 is selected as end address of sequence.
15h = MEMCTL21 is selected as end address of sequence.
16h = MEMCTL22 is selected as end address of sequence.
17h = MEMCTL23 is selected as end address of sequence.
23-21RESERVEDR/W0h
20-16STARTADDR/W0hSequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode.
The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
00h = MEMCTL0 is selected as start address of a sequence or for a single conversion.
01h = MEMCTL1 is selected as start address of a sequence or for a single conversion.
02h = MEMCTL2 is selected as start address of a sequence or for a single conversion.
03h = MEMCTL3 is selected as start address of a sequence or for a single conversion.
04h = MEMCTL4 is selected as start address of a sequence or for a single conversion.
05h = MEMCTL5 is selected as start address of a sequence or for a single conversion.
06h = MEMCTL6 is selected as start address of a sequence or for a single conversion.
07h = MEMCTL7 is selected as start address of a sequence or for a single conversion.
08h = MEMCTL8 is selected as start address of a sequence or for a single conversion.
09h = MEMCTL9 is selected as start address of a sequence or for a single conversion.
0Ah = MEMCTL10 is selected as start address of a sequence or for a single conversion.
0Bh = MEMCTL11 is selected as start address of a sequence or for a single conversion.
0Ch = MEMCTL12 is selected as start address of a sequence or for a single conversion.
0Dh = MEMCTL13 is selected as start address of a sequence or for a single conversion.
0Eh = MEMCTL14 is selected as start address of a sequence or for a single conversion.
0Fh = MEMCTL15 is selected as start address of a sequence or for a single conversion.
10h = MEMCTL16 is selected as start address of a sequence or for a single conversion.
11h = MEMCTL17 is selected as start address of a sequence or for a single conversion.
12h = MEMCTL18 is selected as start address of a sequence or for a single conversion.
13h = MEMCTL19 is selected as start address of a sequence or for a single conversion.
14h = MEMCTL20 is selected as start address of a sequence or for a single conversion.
15h = MEMCTL21 is selected as start address of a sequence or for a single conversion.
16h = MEMCTL22 is selected as start address of a sequence or for a single conversion.
17h = MEMCTL23 is selected as start address of a sequence or for a single conversion.
15-11SAMPCNTR/W0hNumber of ADC converted samples to be transferred on a DMA trigger
0h = Minimum value
18h = Maximum value
10FIFOENR/W0hEnable FIFO based operation
0h = Disable
1h = Enable
9RESERVEDR/W0h
8DMAENRH/W0hEnable DMA trigger for data transfer.
Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
0h (R/W) = DMA trigger not enabled
1h (R/W) = DMA trigger enabled
7-3RESERVEDR/W0h
2-1RESR/W0hResolution. These bits define the resolution of ADC conversion result.
Note : A value of 3 defaults to 12-bits resolution.
0h = 12-bits resolution
1h = 10-bits resolution
2h = 8-bits resolution
0DFR/W0hData read-back format. Data is always stored in binary unsigned format.
0h = Digital result reads as Binary Unsigned.
1h = Digital result reads Signed Binary. (2s complement), left aligned.

10.3.30 CTL3 (Offset = 110Ch) [Reset = 00000000h]

CTL3 is shown in Figure 10-34 and described in Table 10-41.

Return to the Summary Table.

Control Register 3. This register is used to configure ADC for ad-hoc single conversion.

Figure 10-34 CTL3
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVEDASCVRSELRESERVEDASCSTIME
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDASCCHSEL
R/W-0hR/W-0h
Table 10-41 CTL3 Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR/W0h
13-12ASCVRSELR/W0hSelects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDA reference.
1h = EXTREF pin reference.
2h = Internal reference.
11-9RESERVEDR/W0h
8ASCSTIMER/W0hASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
0h = Select SCOMP0
1h = Select SCOMP1
7-5RESERVEDR/W0h
4-0ASCCHSELR/W0hASC channel select
00h = Selects channel 0
01h = Selects channel 1
02h = Selects channel 2
03h = Selects channel 3
04h = Selects channel 4
05h = Selects channel 5
06h = Selects channel 6
07h = Selects channel 7
08h = Selects channel 8
09h = Selects channel 9
0Ah = Selects channel 10
0Bh = Selects channel 11
0Ch = Selects channel 12
0Dh = Selects channel 13
0Eh = Selects channel 14
0Fh = Selects channel 15
10h = Selects channel 16
11h = Selects channel 17
12h = Selects channel 18
13h = Selects channel 19
14h = Selects channel 20
15h = Selects channel 21
16h = Selects channel 22
17h = Selects channel 23
18h = Selects channel 24
19h = Selects channel 25
1Ah = Selects channel 26
1Bh = Selects channel 27
1Ch = Selects channel 28
1Dh = Selects channel 29
1Eh = Selects channel 30
1Fh = Selects channel 31

10.3.31 CLKFREQ (Offset = 1110h) [Reset = 00000000h]

CLKFREQ is shown in Figure 10-35 and described in Table 10-42.

Return to the Summary Table.

Sampling clock frequency range register.

Figure 10-35 CLKFREQ
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDFRANGE
R/W-0hR/W-0h
Table 10-42 CLKFREQ Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0FRANGER/W0hFrequency Range.
0h = 1 to 4 MHz
1h = >4 to 8 MHz
2h = >8 to 16 MHz
3h = >16 to 20 MHz
4h = >20 to 24 MHz
5h = >24 to 32 MHz
6h = >32 to 40 MHz
7h = >40 to 48 MHz

10.3.32 SCOMP0 (Offset = 1114h) [Reset = 00000000h]

SCOMP0 is shown in Figure 10-36 and described in Table 10-43.

Return to the Summary Table.

Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be 0 to write to this register.

Figure 10-36 SCOMP0
313029282726252423222120191817161514131211109876543210
RESERVEDVAL
R/W-0hR/W-0h
Table 10-43 SCOMP0 Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

10.3.33 SCOMP1 (Offset = 1118h) [Reset = 00000000h]

SCOMP1 is shown in Figure 10-37 and described in Table 10-44.

Return to the Summary Table.

Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be 0 to write to this register.

Figure 10-37 SCOMP1
313029282726252423222120191817161514131211109876543210
RESERVEDVAL
R/W-0hR/W-0h
Table 10-44 SCOMP1 Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0h
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

10.3.34 REFCFG (Offset = 111Ch) [Reset = 00000000h]

REFCFG is shown in Figure 10-38 and described in Table 10-45.

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Reference buffer configuration register

Figure 10-38 REFCFG
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDIBPROGRESERVEDREFVSELREFEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-45 REFCFG Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0h
4-3IBPROGR/W0hConfigures reference buffer bias current output value
0h = 1uA
1h = 0.5uA
2h = 2uA
3h = 0.67uA
2RESERVEDR/W0h
1REFVSELR/W0hConfigures reference buffer output voltage
0h = Reference buffer generates 2.5 V output
1h = Reference buffer generates 1.4 V output
0REFENR/W0hReference buffer enable
0h = Disable
1h = Enable

10.3.35 WCLOW (Offset = 1148h) [Reset = 00000000h]

WCLOW is shown in Figure 10-39 and described in Table 10-46.

Return to the Summary Table.

Window Comparator Low Threshold Register.
The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCLOW.

Figure 10-39 WCLOW
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R/W-0hR/W-0h
Table 10-46 WCLOW Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The value based on the resolution has to be right aligned with the MSB on the left.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

10.3.36 WCHIGH (Offset = 1150h) [Reset = 00000000h]

WCHIGH is shown in Figure 10-40 and described in Table 10-47.

Return to the Summary Table.

Window Comparator High Threshold Register.
The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCHIGH.

Figure 10-40 WCHIGH
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R/W-0hR/W-0h
Table 10-47 WCHIGH Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The threshold value has to be right aligned, with the MSB on the left.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

10.3.37 FIFODATA (Offset = 1160h) [Reset = 00000000h]

FIFODATA is shown in Figure 10-41 and described in Table 10-48.

Return to the Summary Table.

FIFO data register. This is a virtual register used to do read from FIFO.

Figure 10-41 FIFODATA
313029282726252423222120191817161514131211109876543210
DATA
R-
Table 10-48 FIFODATA Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hRead from this data field returns the ADC sample from FIFO.

10.3.38 ASCRES (Offset = 1170h) [Reset = 00000000h]

ASCRES is shown in Figure 10-42 and described in Table 10-49.

Return to the Summary Table.

ASC result register

Figure 10-42 ASCRES
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR-0h
Table 10-49 ASCRES Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DATAR0hResult of ADC ad-hoc single conversion.
If DF = 0, unsigned binary:
The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

10.3.39 MEMCTL[y] (Offset = 1180h + formula) [Reset = 00000000h]

MEMCTL[y] is shown in Figure 10-43 and described in Table 10-50.

Return to the Summary Table.

Conversion Memory Control Register.
CTL0.ENC must be 0 to write to this register.

Offset = 1180h + (y * 4h); where y = 0h to 17h

Figure 10-43 MEMCTL[y]
3130292827262524
RESERVEDWINCOMPRESERVEDTRIG
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDBCSENRESERVEDAVGEN
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDSTIMERESERVEDVRSEL
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDCHANSEL
R/W-0hR/W-0h
Table 10-50 MEMCTL[y] Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28WINCOMPR/W0hEnable window comparator.
0h = Disable
1h = Enable
27-25RESERVEDR/W0h
24TRIGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0h = Next conversion is automatic
1h = Next conversion requires a trigger
23-21RESERVEDR/W0h
20BCSENR/W0hEnable burn out current source.
0h = Disable
1h = Enable
19-17RESERVEDR/W0h
16AVGENR/W0hEnable hardware averaging.
0h (R/W) = Averaging disabled.
1h = Averaging enabled.
15-13RESERVEDR/W0h
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
0h = Select SCOMP0
1h = Select SCOMP1
11-10RESERVEDR/W0h
9-8VRSELR/W0hVoltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDA reference
1h = External reference from pin
2h = Internal reference
7-5RESERVEDR/W0h
4-0CHANSELR/W0hInput channel select.
00h = Selects channel 0
01h = Selects channel 1
02h = Selects channel 2
03h = Selects channel 3
04h = Selects channel 4
05h = Selects channel 5
06h = Selects channel 6
07h = Selects channel 7
08h = Selects channel 8
09h = Selects channel 9
0Ah = Selects channel 10
0Bh = Selects channel 11
0Ch = Selects channel 12
0Dh = Selects channel 13
0Eh = Selects channel 14
0Fh = Selects channel 15
10h = Selects channel 16
11h = Selects channel 17
12h = Selects channel 18
13h = Selects channel 19
14h = Selects channel 20
15h = Selects channel 21
16h = Selects channel 22
17h = Selects channel 23
18h = Selects channel 24
19h = Selects channel 25
1Ah = Selects channel 26
1Bh = Selects channel 27
1Ch = Selects channel 28
1Dh = Selects channel 29
1Eh = Selects channel 30
1Fh = Selects channel 31

10.3.40 MEMRES[y] (Offset = 1280h + formula) [Reset = 00000000h]

MEMRES[y] is shown in Figure 10-44 and described in Table 10-51.

Return to the Summary Table.

Memory Result Register

Offset = 1280h + (y * 4h); where y = 0h to 17h

Figure 10-44 MEMRES[y]
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-R-
Table 10-51 MEMRES[y] Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DATAR0hMEMRES result register.
If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

10.3.41 STATUS (Offset = 1340h) [Reset = 00000000h]

STATUS is shown in Figure 10-45 and described in Table 10-52.

Return to the Summary Table.

Status Register

Figure 10-45 STATUS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDASCACTREFBUFRDYBUSY
R-0hR-0hR-0hR-0h
Table 10-52 STATUS Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2ASCACTR0hASC active
0h = Idle or done
1h = ASC active
1REFBUFRDYR0hIndicates reference buffer is powered up and ready.
0h = Not ready
1h = Ready
0BUSYR0hBusy. This bit indicates that an active ADC sample or conversion operation is in progress.
0h = No ADC sampling or conversion in progress.
1h = ADC sampling or conversion is in progress.