SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

2.6 SYSCTL Registers

Table 2-20 lists the memory-mapped registers for the SYSCTL registers. All register offset addresses not listed in Table 2-20 should be considered as reserved locations and the register contents should not be modified.

Table 2-20 SYSCTL Registers
OffsetAcronymRegister NameSection
1020hIIDXSYSCTL interrupt indexSection 2.6.1
1028hIMASKSYSCTL interrupt maskSection 2.6.2
1030hRISSYSCTL raw interrupt statusSection 2.6.3
1038hMISSYSCTL masked interrupt statusSection 2.6.4
1040hISETSYSCTL interrupt setSection 2.6.5
1048hICLRSYSCTL interrupt clearSection 2.6.6
1050hNMIIIDXNMI interrupt indexSection 2.6.7
1060hNMIRISNMI raw interrupt statusSection 2.6.8
1070hNMIISETNMI interrupt setSection 2.6.9
1078hNMIICLRNMI interrupt clearSection 2.6.10
1100hSYSOSCCFGSYSOSC configurationSection 2.6.11
1104hMCLKCFGMain clock (MCLK) configurationSection 2.6.12
1108hHSCLKENHigh-speed clock (HSCLK) source enable/disableSection 2.6.13
110ChHSCLKCFGHigh-speed clock (HSCLK) source selectionSection 2.6.14
1110hHFCLKCLKCFGHigh-frequency clock (HFCLK) configurationSection 2.6.15
1114hLFCLKCFGLow frequency crystal oscillator (LFXT) configurationSection 2.6.16
1120hSYSPLLCFG0SYSPLL reference and output configurationSection 2.6.17
1124hSYSPLLCFG1SYSPLL reference and feedback dividerSection 2.6.18
1128hSYSPLLPARAM0SYSPLL PARAM0 (load from FACTORY region)Section 2.6.19
112ChSYSPLLPARAM1SYSPLL PARAM1 (load from FACTORY region)Section 2.6.20
1138hGENCLKCFGGeneral clock configurationSection 2.6.21
113ChGENCLKENGeneral clock enable controlSection 2.6.22
1140hPMODECFGPower mode configurationSection 2.6.23
1150hFCCFrequency clock counter (FCC) countSection 2.6.24
1170hSYSOSCTRIMUSERSYSOSC user-specified trimSection 2.6.25
1178hSRAMBOUNDARYSRAM Write BoundarySection 2.6.26
1180hSYSTEMCFGSystem configurationSection 2.6.27
1200hWRITELOCKSYSCTL register write lockoutSection 2.6.28
1204hCLKSTATUSClock module (CKM) statusSection 2.6.29
1208hSYSSTATUSSystem status informationSection 2.6.30
120ChDEDERRADDRMemory DED AddressSection 2.6.31
1220hRSTCAUSEReset causeSection 2.6.32
1300hRESETLEVELReset level for application-triggered reset commandSection 2.6.33
1304hRESETCMDExecute an application-triggered reset commandSection 2.6.34
1308hBORTHRESHOLDBOR threshold selectionSection 2.6.35
130ChBORCLRCMDSet the BOR thresholdSection 2.6.36
1310hSYSOSCFCLCTLSYSOSC frequency correction loop (FCL) ROSC enableSection 2.6.37
1314hLFXTCTLLFXT and LFCLK controlSection 2.6.38
1318hEXLFCTLLFCLK_IN and LFCLK controlSection 2.6.39
131ChSHDNIORELSHUTDOWN IO release controlSection 2.6.40
1320hEXRSTPINDisable the reset function of the NRST pinSection 2.6.41
1324hSYSSTATUSCLRClear sticky bits of SYSSTATUSSection 2.6.42
1328hSWDCFGDisable the SWD function on the SWD pinsSection 2.6.43
132ChFCCCMDFrequency clock counter start captureSection 2.6.44
1380hPMUOPAMPGPAMP controlSection 2.6.45
1400hSHUTDNSTORE0Shutdown storage memory (byte 0)Section 2.6.46
1404hSHUTDNSTORE1Shutdown storage memory (byte 1)Section 2.6.47
1408hSHUTDNSTORE2Shutdown storage memory (byte 2)Section 2.6.48
140ChSHUTDNSTORE3Shutdown storage memory (byte 3)Section 2.6.49

Complex bit access types are encoded to fit into small table cells. Table 2-21 shows the codes that are used for access types in this section.

Table 2-21 SYSCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value

2.6.1 IIDX Register (Offset = 1020h) [Reset = X]

IIDX is shown in Figure 2-12 and described in Table 2-22.

Return to the Table 2-20.

SYSCTL interrupt index

Figure 2-12 IIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-XR-0h
Table 2-22 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3-0STATR0hThe SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
0h = No interrupt pending
1h = LFOSCGOOD interrupt pending
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8

2.6.2 IMASK Register (Offset = 1028h) [Reset = X]

IMASK is shown in Figure 2-13 and described in Table 2-23.

Return to the Table 2-20.

SYSCTL interrupt mask

Figure 2-13 IMASK Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
HSCLKGOODSYSPLLGOODHFCLKGOODLFXTGOODSRAMSECFLASHSECANACLKERRLFOSCGOOD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 2-23 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7HSCLKGOODR/W0hHSCLK GOOD
0h = 0
1h = 1
6SYSPLLGOODR/W0hSYSPLL GOOD
0h = 0
1h = 1
5HFCLKGOODR/W0hHFCLK GOOD
0h = 0
1h = 1
4LFXTGOODR/W0hLFXT GOOD
0h = 0
1h = 1
3SRAMSECR/W0hSRAM Single Error Correct
0h = 0
1h = 1
2FLASHSECR/W0hFlash Single Error Correct
0h = 0
1h = 1
1ANACLKERRR/W0hAnalog Clocking Consistency Error
0h = 0
1h = 1
0LFOSCGOODR/W0hEnable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.
0h = Interrupt disabled
1h = Interrupt enabled

2.6.3 RIS Register (Offset = 1030h) [Reset = X]

RIS is shown in Figure 2-14 and described in Table 2-24.

Return to the Table 2-20.

SYSCTL raw interrupt status

Figure 2-14 RIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
HSCLKGOODSYSPLLGOODHFCLKGOODLFXTGOODSRAMSECFLASHSECANACLKERRLFOSCGOOD
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 2-24 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7HSCLKGOODR0hHSCLK GOOD
0h = 0
1h = 1
6SYSPLLGOODR0hSYSPLL GOOD
0h = 0
1h = 1
5HFCLKGOODR0hHFCLK GOOD
0h = 0
1h = 1
4LFXTGOODR0hLFXT GOOD
0h = 0
1h = 1
3SRAMSECR0hSRAM Single Error Correct
0h = 0
1h = 1
2FLASHSECR0hFlash Single Error Correct
0h = 0
1h = 1
1ANACLKERRR0hAnalog Clocking Consistency Error
0h = 0
1h = 1
0LFOSCGOODR0hRaw status of the LFOSCGOOD interrupt.
0h = No interrupt pending
1h = Interrupt pending

2.6.4 MIS Register (Offset = 1038h) [Reset = X]

MIS is shown in Figure 2-15 and described in Table 2-25.

Return to the Table 2-20.

SYSCTL masked interrupt status

Figure 2-15 MIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
HSCLKGOODSYSPLLGOODHFCLKGOODLFXTGOODSRAMSECFLASHSECANACLKERRLFOSCGOOD
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 2-25 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7HSCLKGOODR0hHSCLK GOOD
0h = 0
1h = 1
6SYSPLLGOODR0hSYSPLL GOOD
0h = 0
1h = 1
5HFCLKGOODR0hHFCLK GOOD
0h = 0
1h = 1
4LFXTGOODR0hLFXT GOOD
0h = 0
1h = 1
3SRAMSECR0hSRAM Single Error Correct
0h = 0
1h = 1
2FLASHSECR0hFlash Single Error Correct
0h = 0
1h = 1
1ANACLKERRR0hAnalog Clocking Consistency Error
0h = 0
1h = 1
0LFOSCGOODR0hMasked status of the LFOSCGOOD interrupt.
0h = No interrupt pending
1h = Interrupt pending

2.6.5 ISET Register (Offset = 1040h) [Reset = X]

ISET is shown in Figure 2-16 and described in Table 2-26.

Return to the Table 2-20.

SYSCTL interrupt set

Figure 2-16 ISET Register
3130292827262524
RESERVED
W-X
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
HSCLKGOODSYSPLLGOODHFCLKGOODLFXTGOODSRAMSECFLASHSECANACLKERRLFOSCGOOD
W1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
Table 2-26 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDWX
7HSCLKGOODW1S0hHSCLK GOOD
0h = 0
1h = 1
6SYSPLLGOODW1S0hSYSPLL GOOD
0h = 0
1h = 1
5HFCLKGOODW1S0hHFCLK GOOD
0h = 0
1h = 1
4LFXTGOODW1S0hLFXT GOOD
0h = 0
1h = 1
3SRAMSECW1S0hSRAM Single Error Correct
0h = 0
1h = 1
2FLASHSECW1S0hFlash Single Error Correct
0h = 0
1h = 1
1ANACLKERRW1S0hAnalog Clocking Consistency Error
0h = 0
1h = 1
0LFOSCGOODW1S0hSet the LFOSCGOOD interrupt.
0h = Writing 0h has no effect
1h = Set interrupt

2.6.6 ICLR Register (Offset = 1048h) [Reset = X]

ICLR is shown in Figure 2-17 and described in Table 2-27.

Return to the Table 2-20.

SYSCTL interrupt clear

Figure 2-17 ICLR Register
3130292827262524
RESERVED
W-X
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
HSCLKGOODSYSPLLGOODHFCLKGOODLFXTGOODSRAMSECFLASHSECANACLKERRLFOSCGOOD
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
Table 2-27 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDWX
7HSCLKGOODW1C0hHSCLK GOOD
0h = 0
1h = 1
6SYSPLLGOODW1C0hSYSPLL GOOD
0h = 0
1h = 1
5HFCLKGOODW1C0hHFCLK GOOD
0h = 0
1h = 1
4LFXTGOODW1C0hLFXT GOOD
0h = 0
1h = 1
3SRAMSECW1C0hSRAM Single Error Correct
0h = 0
1h = 1
2FLASHSECW1C0hFlash Single Error Correct
0h = 0
1h = 1
1ANACLKERRW1C0hAnalog Clocking Consistency Error
0h = 0
1h = 1
0LFOSCGOODW1C0hClear the LFOSCGOOD interrupt.
0h = Writing 0h has no effect
1h = Clear interrupt

2.6.7 NMIIIDX Register (Offset = 1050h) [Reset = X]

NMIIIDX is shown in Figure 2-18 and described in Table 2-28.

Return to the Table 2-20.

NMI interrupt index

Figure 2-18 NMIIIDX Register
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-XR-0h
Table 2-28 NMIIIDX Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3-0STATR0hThe NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.
0h = No NMI pending
1h = BOR Threshold NMI pending
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6

2.6.8 NMIRIS Register (Offset = 1060h) [Reset = X]

NMIRIS is shown in Figure 2-19 and described in Table 2-29.

Return to the Table 2-20.

NMI raw interrupt status

Figure 2-19 NMIRIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDSRAMDEDFLASHDEDLFCLKFAILWWDT1WWDT0BORLVL
R-XR-0hR-0hR-0hR-0hR-0hR-0h
Table 2-29 NMIRIS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDRX
5SRAMDEDR0hSRAM Double Error Detect
0h = 0
1h = 1
4FLASHDEDR0hFlash Double Error Detect
0h = 0
1h = 1
3LFCLKFAILR0hLFXT-EXLF Monitor Fail
0h = 0
1h = 1
2WWDT1R0hWatch Dog 0 Fault
0h = 0
1h = 1
1WWDT0R0hWatch Dog 0 Fault
0h = 0
1h = 1
0BORLVLR0hRaw status of the BORLVL NMI
0h = No interrupt pending
1h = Interrupt pending

2.6.9 NMIISET Register (Offset = 1070h) [Reset = X]

NMIISET is shown in Figure 2-20 and described in Table 2-30.

Return to the Table 2-20.

NMI interrupt set

Figure 2-20 NMIISET Register
3130292827262524
RESERVED
W-X
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDSRAMDEDFLASHDEDLFCLKFAILWWDT1WWDT0BORLVL
W-XW1S-0hW1S-0hW1S-0hW1S-0hW1S-0hW1S-0h
Table 2-30 NMIISET Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDWX
5SRAMDEDW1S0hSRAM Double Error Detect
0h = 0
1h = 1
4FLASHDEDW1S0hFlash Double Error Detect
0h = 0
1h = 1
3LFCLKFAILW1S0hLFXT-EXLF Monitor Fail
0h = 0
1h = 1
2WWDT1W1S0hWatch Dog 0 Fault
0h = 0
1h = 1
1WWDT0W1S0hWatch Dog 0 Fault
0h = 0
1h = 1
0BORLVLW1S0hSet the BORLVL NMI
0h = Writing 0h has no effect
1h = Set interrupt

2.6.10 NMIICLR Register (Offset = 1078h) [Reset = X]

NMIICLR is shown in Figure 2-21 and described in Table 2-31.

Return to the Table 2-20.

NMI interrupt clear

Figure 2-21 NMIICLR Register
3130292827262524
RESERVED
W-X
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDSRAMDEDFLASHDEDLFCLKFAILWWDT1WWDT0BORLVL
W-XW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
Table 2-31 NMIICLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDWX
5SRAMDEDW1C0hSRAM Double Error Detect
0h = 0
1h = 1
4FLASHDEDW1C0hFlash Double Error Detect
0h = 0
1h = 1
3LFCLKFAILW1C0hLFXT-EXLF Monitor Fail
0h = 0
1h = 1
2WWDT1W1C0hWatch Dog 0 Fault
0h = 0
1h = 1
1WWDT0W1C0hWatch Dog 0 Fault
0h = 0
1h = 1
0BORLVLW1C0hClear the BORLVL NMI
0h = Writing 0h has no effect
1h = Clear interrupt

2.6.11 SYSOSCCFG Register (Offset = 1100h) [Reset = X]

SYSOSCCFG is shown in Figure 2-22 and described in Table 2-32.

Return to the Table 2-20.

SYSOSC configuration

Figure 2-22 SYSOSCCFG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDFASTCPUEVENTBLOCKASYNCALL
R/W-XR/W-1hR/W-0h
15141312111098
RESERVEDDISABLEDISABLESTOPUSE4MHZSTOP
R/W-XR/W-0hR/W-0hR/W-0h
76543210
RESERVEDFREQ
R/W-XR/W-0h
Table 2-32 SYSOSCCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/WX
17FASTCPUEVENTR/W1hFASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.
0h = An interrupt to the CPU will not assert a fast clock request
1h = An interrupt to the CPU will assert a fast clock request
16BLOCKASYNCALLR/W0hBLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.
0h = Asynchronous fast clock requests are controlled by the requesting peripheral
1h = All asynchronous fast clock requests are blocked
15-11RESERVEDR/WX
10DISABLER/W0hDISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.
0h = Do not disable SYSOSC
1h = Disable SYSOSC immediately and source MCLK and ULPCLK from LFCLK
9DISABLESTOPR/W0hDISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.
0h = Do not disable SYSOSC in STOP mode
1h = Disable SYSOSC in STOP mode and source ULPCLK from LFCLK
8USE4MHZSTOPR/W0hUSE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.
0h = Do not gear shift the SYSOSC to 4MHz in STOP mode
1h = Gear shift SYSOSC to 4MHz in STOP mode
7-2RESERVEDR/WX
1-0FREQR/W0hTarget operating frequency for the system oscillator (SYSOSC)
0h = Base frequency (32MHz)
1h = Low frequency (4MHz)
2h = User-trimmed frequency (16 or 24 MHz)

2.6.12 MCLKCFG Register (Offset = 1104h) [Reset = X]

MCLKCFG is shown in Figure 2-23 and described in Table 2-33.

Return to the Table 2-20.

Main clock (MCLK) configuration

Figure 2-23 MCLKCFG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDMCLKDEADCHKSTOPCLKSTBYUSELFCLKRESERVEDUSEHSCLK
R/W-XR/W-0hR/W-0hR/W-0hR/W-XR/W-0h
15141312111098
RESERVEDUSEMFTICKFLASHWAIT
R/W-XR/W-0hR/W-2h
76543210
RESERVEDUDIVMDIV
R/W-XR/W-1hR/W-0h
Table 2-33 MCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/WX
22MCLKDEADCHKR/W0hMCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled.
0h = The MCLK dead check monitor is disabled
1h = The MCLK dead check monitor is enabled
21STOPCLKSTBYR/W0hSTOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request.
0h = ULPCLK/LFCLK runs to all PD0 peripherals in STANDBY mode
1h = ULPCLK/LFCLK is disabled to all peripherals in STANDBY mode except TIMG0 and TIMG1
20USELFCLKR/W0hUSELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source. Note that setting USELFCLK does not disable SYSOSC, and SYSOSC remains available for direct use by analog modules.
0h = MCLK will not use the low frequency clock (LFCLK)
1h = MCLK will use the low frequency clock (LFCLK)
19-17RESERVEDR/WX
16USEHSCLKR/W0hUSEHSCLK, together with USELFCLK, sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes.
0h = MCLK will not use the high speed clock (HSCLK)
1h = MCLK will use the high speed clock (HSCLK) in RUN and SLEEP mode
15-13RESERVEDR/WX
12USEMFTICKR/W0hUSEMFTICK specifies whether the 4MHz constant-rate clock (MFCLK) to peripherals is enabled or disabled. When enabled, MDIV must be disabled (set to 0h=/1).
0h = The 4MHz rate MFCLK to peripherals is enabled
1h = The 4MHz rate MFCLK to peripherals is enabled.
11-8FLASHWAITR/W2hFLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK.
0h = No flash wait states are applied
1h = One flash wait state is applied
2h = 2 flash wait states are applied
7-6RESERVEDR/WX
5-4UDIVR/W1hUDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK.
0h = ULPCLK is not divided and is equal to MCLK
1h = ULPCLK is MCLK/2 (divided-by-2)
2h = ULPCLK is MCLK/3 (divided-by-3)
3-0MDIVR/W0hMDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC. MDIV=0h corresponds to /1 (no divider). MDIV=1h corresponds to /2 (divide-by-2). MDIV=Fh corresponds to /16 (divide-by-16). MDIV may be set between /1 and /16 on an integer basis.

2.6.13 HSCLKEN Register (Offset = 1108h) [Reset = X]

HSCLKEN is shown in Figure 2-24 and described in Table 2-34.

Return to the Table 2-20.

High-speed clock (HSCLK) source enable/disable

Figure 2-24 HSCLKEN Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDUSEEXTHFCLK
R/W-XR/W-0h
15141312111098
RESERVEDSYSPLLEN
R/W-XR/W-0h
76543210
RESERVEDHFXTEN
R/W-XR/W-0h
Table 2-34 HSCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/WX
16USEEXTHFCLKR/W0hUSEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled, HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously.
0h = Use HFXT as the HFCLK source
1h = Use the HFCLK_IN digital clock input as the HFCLK source
15-9RESERVEDR/WX
8SYSPLLENR/W0hSYSPLLEN enables or disables the system phase-lock loop (SYSPLL).
0h = Disable the SYSPLL
1h = Enable the SYSPLL
7-1RESERVEDR/WX
0HFXTENR/W0hHFXTEN enables or disables the high frequency crystal oscillator (HFXT).
0h = Disable the HFXT
1h = Enable the HFXT

2.6.14 HSCLKCFG Register (Offset = 110Ch) [Reset = X]

HSCLKCFG is shown in Figure 2-25 and described in Table 2-35.

Return to the Table 2-20.

High-speed clock (HSCLK) source selection

Figure 2-25 HSCLKCFG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDHSCLKSEL
R/W-XR/W-0h
Table 2-35 HSCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/WX
0HSCLKSELR/W0hHSCLKSEL selects the HSCLK source (SYSPLL or HFCLK).
0h = HSCLK is sourced from the SYSPLL
1h = HSCLK is sourced from the HFCLK

2.6.15 HFCLKCLKCFG Register (Offset = 1110h) [Reset = X]

HFCLKCLKCFG is shown in Figure 2-26 and described in Table 2-36.

Return to the Table 2-20.

High-frequency clock (HFCLK) configuration

Figure 2-26 HFCLKCLKCFG Register
3130292827262524
RESERVEDHFCLKFLTCHKRESERVED
R/W-XR/W-1hR/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDHFXTRSELRESERVED
R/W-XR/W-0hR/W-X
76543210
HFXTTIME
R/W-0h
Table 2-36 HFCLKCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28HFCLKFLTCHKR/W1hHFCLKFLTCHK enables or disables the HFCLK startup monitor.
0h = HFCLK startup is not checked
1h = HFCLK startup is checked
27-14RESERVEDR/WX
13-12HFXTRSELR/W0hHFXT Range Select
0h = 4MHz ≤ HFXT frequency ≤ 8MHz
1h = 8MHz < HFXT frequency ≤ 16MHz
2h = 16MHz < HFXT frequency ≤ 32MHz
3h = 32MHz < HFXT frequency ≤ 48MHz
11-8RESERVEDR/WX
7-0HFXTTIMER/W0hHFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time expires.
0h = Minimum startup time (approximately zero)
FFh = Maximum startup time (approximately 16.32ms)

2.6.16 LFCLKCFG Register (Offset = 1114h) [Reset = X]

LFCLKCFG is shown in Figure 2-27 and described in Table 2-37.

Return to the Table 2-20.

Low frequency crystal oscillator (LFXT) configuration

Figure 2-27 LFCLKCFG Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDLOWCAP
R/W-XR/W-0h
76543210
RESERVEDMONITORRESERVEDXT1DRIVE
R/W-XR/W-0hR/W-XR/W-3h
Table 2-37 LFCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/WX
8LOWCAPR/W0hLOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf, LOWCAP may be set for reduced power consumption.
0h = LFXT low capacitance mode is disabled
1h = LFXT low capacitance mode is enabled
7-5RESERVEDR/WX
4MONITORR/W0hMONITOR enables or disables the LFCLK monitor, which continuously checks LFXT or LFCLK_IN for a clock stuck fault.
0h = Clock monitor is disabled
1h = Clock monitor is enabled
3-2RESERVEDR/WX
1-0XT1DRIVER/W3hXT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength.
0h = Lowest drive and current
1h = Lower drive and current
2h = Higher drive and current
3h = Highest drive and current

2.6.17 SYSPLLCFG0 Register (Offset = 1120h) [Reset = X]

SYSPLLCFG0 is shown in Figure 2-28 and described in Table 2-38.

Return to the Table 2-20.

SYSPLL reference and output configuration

Figure 2-28 SYSPLLCFG0 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDRDIVCLK2X
R/W-XR/W-0h
15141312111098
RDIVCLK1RDIVCLK0
R/W-0hR/W-0h
76543210
RESERVEDENABLECLK2XENABLECLK1ENABLECLK0RESERVEDMCLK2XVCOSYSPLLREF
R/W-XR/W-0hR/W-0hR/W-0hR/W-XR/W-0hR/W-0h
Table 2-38 SYSPLLCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-16RDIVCLK2XR/W0hRDIVCLK2X sets the final divider for the SYSPLLCLK2X output.
0h = SYSPLLCLK1 is divided by 1
1h = SYSPLLCLK1 is divided by 2
2h = SYSPLLCLK1 is divided by 3
3h = SYSPLLCLK1 is divided by 4
4h = SYSPLLCLK1 is divided by 5
5h = SYSPLLCLK1 is divided by 6
6h = SYSPLLCLK1 is divided by 7
7h = SYSPLLCLK1 is divided by 8
8h = SYSPLLCLK1 is divided by 9
9h = SYSPLLCLK1 is divided by 10
Ah = SYSPLLCLK1 is divided by 11
Bh = SYSPLLCLK1 is divided by 12
Ch = SYSPLLCLK1 is divided by 13
Dh = SYSPLLCLK1 is divided by 14
Eh = SYSPLLCLK1 is divided by 15
Fh = SYSPLLCLK1 is divided by 16
15-12RDIVCLK1R/W0hRDIVCLK1 sets the final divider for the SYSPLLCLK1 output.
0h = SYSPLLCLK1 is divided by 2
1h = SYSPLLCLK1 is divided by 4
2h = SYSPLLCLK1 is divided by 6
3h = SYSPLLCLK1 is divided by 8
4h = SYSPLLCLK1 is divided by 10
5h = SYSPLLCLK1 is divided by 12
6h = SYSPLLCLK1 is divided by 14
7h = SYSPLLCLK1 is divided by 16
8h = SYSPLLCLK1 is divided by 18
9h = SYSPLLCLK1 is divided by 20
Ah = SYSPLLCLK1 is divided by 22
Bh = SYSPLLCLK1 is divided by 24
Ch = SYSPLLCLK1 is divided by 26
Dh = SYSPLLCLK1 is divided by 28
Eh = SYSPLLCLK1 is divided by 30
Fh = SYSPLLCLK1 is divided by 32
11-8RDIVCLK0R/W0hRDIVCLK0 sets the final divider for the SYSPLLCLK0 output.
0h = SYSPLLCLK0 is divided by 2
1h = SYSPLLCLK0 is divided by 4
2h = SYSPLLCLK0 is divided by 6
3h = SYSPLLCLK0 is divided by 8
4h = SYSPLLCLK0 is divided by 10
5h = SYSPLLCLK0 is divided by 12
6h = SYSPLLCLK0 is divided by 14
7h = SYSPLLCLK0 is divided by 16
8h = SYSPLLCLK0 is divided by 18
9h = SYSPLLCLK0 is divided by 20
Ah = SYSPLLCLK0 is divided by 22
Bh = SYSPLLCLK0 is divided by 24
Ch = SYSPLLCLK0 is divided by 26
Dh = SYSPLLCLK0 is divided by 28
Eh = SYSPLLCLK0 is divided by 30
Fh = SYSPLLCLK0 is divided by 32
7RESERVEDR/WX
6ENABLECLK2XR/W0hENABLECLK2X enables or disables the SYSPLLCLK2X output.
0h = SYSPLLCLK2X is disabled
1h = SYSPLLCLK2X is enabled
5ENABLECLK1R/W0hENABLECLK1 enables or disables the SYSPLLCLK1 output.
0h = SYSPLLCLK1 is disabled
1h = SYSPLLCLK1 is enabled
4ENABLECLK0R/W0hENABLECLK0 enables or disables the SYSPLLCLK0 output.
0h = SYSPLLCLK0 is disabled
1h = SYSPLLCLK0 is enabled
3-2RESERVEDR/WX
1MCLK2XVCOR/W0hMCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK.
0h = The SYSPLLCLK0 output is sent to the HSCLK mux
1h = The SYSPLLCLK2X output is sent to the HSCLK mux
0SYSPLLREFR/W0hSYSPLLREF selects the system PLL (SYSPLL) reference clock source.
0h = SYSPLL reference is SYSOSC
1h = SYSPLL reference is HFCLK

2.6.18 SYSPLLCFG1 Register (Offset = 1124h) [Reset = X]

SYSPLLCFG1 is shown in Figure 2-29 and described in Table 2-39.

Return to the Table 2-20.

SYSPLL reference and feedback divider

Figure 2-29 SYSPLLCFG1 Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDQDIVRESERVEDPDIV
R/W-XR/W-0hR/W-XR/W-0h
Table 2-39 SYSPLLCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/WX
14-8QDIVR/W0hQDIV selects the SYSPLL feedback path divider.
0h = Divide-by-one is not a valid QDIV option
1h = Feedback path is divided by 2
7Eh = Feedback path is divided by 127 (0x7E)
7-2RESERVEDR/WX
1-0PDIVR/W0hPDIV selects the SYSPLL reference clock prescale divider.
0h = SYSPLLREF is not divided
1h = SYSPLLREF is divided by 2
2h = SYSPLLREF is divided by 4
3h = SYSPLLREF is divided by 8

2.6.19 SYSPLLPARAM0 Register (Offset = 1128h) [Reset = X]

SYSPLLPARAM0 is shown in Figure 2-30 and described in Table 2-40.

Return to the Table 2-20.

SYSPLL PARAM0 (load from FACTORY region)

Figure 2-30 SYSPLLPARAM0 Register
3130292827262524
CAPBOVERRIDERESERVEDCAPBVAL
R/W-0hR/W-XR/W-0h
2322212019181716
RESERVEDCPCURRENT
R/W-XR/W-0h
15141312111098
RESERVEDSTARTTIMELP
R/W-XR/W-0h
76543210
RESERVEDSTARTTIME
R/W-XR/W-0h
Table 2-40 SYSPLLPARAM0 Register Field Descriptions
BitFieldTypeResetDescription
31CAPBOVERRIDER/W0hCAPBOVERRIDE controls the override for Cap B
0h = Cap B override disabled
1h = Cap B override enabled
30-29RESERVEDR/WX
28-24CAPBVALR/W0hOverride value for Cap B
23-22RESERVEDR/WX
21-16CPCURRENTR/W0hCharge pump current
15-14RESERVEDR/WX
13-8STARTTIMELPR/W0hStartup time from low power mode exit to locked clock, in 1us resolution
7-6RESERVEDR/WX
5-0STARTTIMER/W0hStartup time from enable to locked clock, in 1us resolution

2.6.20 SYSPLLPARAM1 Register (Offset = 112Ch) [Reset = X]

SYSPLLPARAM1 is shown in Figure 2-31 and described in Table 2-41.

Return to the Table 2-20.

SYSPLL PARAM1 (load from FACTORY region)

Figure 2-31 SYSPLLPARAM1 Register
31302928272625242322212019181716
LPFRESCRESERVEDLPFRESA
R/W-0hR/W-XR/W-0h
1514131211109876543210
LPFRESARESERVEDLPFCAPA
R/W-0hR/W-XR/W-0h
Table 2-41 SYSPLLPARAM1 Register Field Descriptions
BitFieldTypeResetDescription
31-24LPFRESCR/W0hLoop filter Res C
23-18RESERVEDR/WX
17-8LPFRESAR/W0hLoop filter Res A
7-5RESERVEDR/WX
4-0LPFCAPAR/W0hLoop filter Cap A

2.6.21 GENCLKCFG Register (Offset = 1138h) [Reset = X]

GENCLKCFG is shown in Figure 2-32 and described in Table 2-42.

Return to the Table 2-20.

General clock configuration

Figure 2-32 GENCLKCFG Register
3130292827262524
RESERVEDFCCTRIGCNT
R/W-XR/W-0h
2322212019181716
ANACPUMPCFGFCCLVLTRIGFCCTRIGSRCFCCSELCLK
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
HFCLK4MFPCLKDIVRESERVEDMFPCLKSRCCANCLKSRC
R/W-0hR/W-XR/W-0hR/W-0h
76543210
EXCLKDIVENEXCLKDIVVALRESERVEDEXCLKSRC
R/W-0hR/W-0hR/W-XR/W-0h
Table 2-42 GENCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24FCCTRIGCNTR/W0hFCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified.
23-22ANACPUMPCFGR/W0hANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method.
0h = VBOOST is enabled on request from a COMP, GPAMP, or OPA
1h = VBOOST is enabled when the device is in RUN or SLEEP mode, or when a COMP/GPAMP/OPA is enabled
2h = VBOOST is always enabled
21FCCLVLTRIGR/W0hFCCLVLTRIG selects the frequency clock counter (FCC) trigger mode.
0h = Rising edge to rising edge triggered
1h = Level triggered
20FCCTRIGSRCR/W0hFCCTRIGSRC selects the frequency clock counter (FCC) trigger source.
0h = FCC trigger is the external pin
1h = FCC trigger is the LFCLK
19-16FCCSELCLKR/W0hFCCSELCLK selects the frequency clock counter (FCC) clock source.
0h = FCC clock is MCLK
1h = FCC clock is SYSOSC
2h = FCC clock is HFCLK
3h = FCC clock is the CLK_OUT selection
4h = FCC clock is SYSPLLCLK0
5h = FCC clock is SYSPLLCLK1
6h = FCC clock is SYSPLLCLK2X
7h = FCC clock is the FCCIN external input
15-12HFCLK4MFPCLKDIVR/W0hHFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected.
0h = HFCLK is not divided before being used for MFPCLK
1h = HFCLK is divided by 2 before being used for MFPCLK
2h = HFCLK is divided by 3 before being used for MFPCLK
3h = HFCLK is divided by 4 before being used for MFPCLK
4h = HFCLK is divided by 5 before being used for MFPCLK
5h = HFCLK is divided by 6 before being used for MFPCLK
6h = HFCLK is divided by 7 before being used for MFPCLK
7h = HFCLK is divided by 8 before being used for MFPCLK
8h = HFCLK is divided by 9 before being used for MFPCLK
9h = HFCLK is divided by 10 before being used for MFPCLK
Ah = HFCLK is divided by 11 before being used for MFPCLK
Bh = HFCLK is divided by 12 before being used for MFPCLK
Ch = HFCLK is divided by 13 before being used for MFPCLK
Dh = HFCLK is divided by 14 before being used for MFPCLK
Eh = HFCLK is divided by 15 before being used for MFPCLK
Fh = HFCLK is divided by 16 before being used for MFPCLK
11-10RESERVEDR/WX
9MFPCLKSRCR/W0hMFPCLKSRC selects the MFPCLK (middle frequency precision clock) source.
0h = MFPCLK is sourced from SYSOSC
1h = MFPCLK is sourced from HFCLK
8CANCLKSRCR/W0hCANCLKSRC selects the CANCLK source.
0h = CANCLK source is HFCLK
1h = CANCLK source is SYSPLLCLK1
7EXCLKDIVENR/W0hEXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block.
0h = Clock divider is disabled (pass through, EXCLKDIVVAL is not applied)
1h = Clock divider is enabled (EXCLKDIVVAL is applied)
6-4EXCLKDIVVALR/W0hEXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block.
0h = CLK_OUT source is divided by 2
1h = CLK_OUT source is divided by 4
2h = CLK_OUT source is divided by 6
3h = CLK_OUT source is divided by 8
4h = CLK_OUT source is divided by 10
5h = CLK_OUT source is divided by 12
6h = CLK_OUT source is divided by 14
7h = CLK_OUT source is divided by 16
3RESERVEDR/WX
2-0EXCLKSRCR/W0hEXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled
0h = CLK_OUT is SYSOSC
1h = CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled)
2h = CLK_OUT is LFCLK
3h = CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled)
4h = CLK_OUT is HFCLK
5h = CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be ≤48MHz)

2.6.22 GENCLKEN Register (Offset = 113Ch) [Reset = X]

GENCLKEN is shown in Figure 2-33 and described in Table 2-43.

Return to the Table 2-20.

General clock enable control

Figure 2-33 GENCLKEN Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDMFPCLKENRESERVEDEXCLKEN
R/W-XR/W-0hR/W-XR/W-0h
Table 2-43 GENCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/WX
4MFPCLKENR/W0hMFPCLKEN enables the middle frequency precision clock (MFPCLK).
0h = MFPCLK is disabled
1h = MFPCLK is enabled
3-1RESERVEDR/WX
0EXCLKENR/W0hEXCLKEN enables the CLK_OUT external clock output block.
0h = CLK_OUT block is disabled
1h = CLK_OUT block is enabled

2.6.23 PMODECFG Register (Offset = 1140h) [Reset = X]

PMODECFG is shown in Figure 2-34 and described in Table 2-44.

Return to the Table 2-20.

Power mode configuration

Figure 2-34 PMODECFG Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDDSLEEP
R/W-XR/W-0h
Table 2-44 PMODECFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/WX
1-0DSLEEPR/W0hDSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.
0h = STOP mode is entered
1h = STANDBY mode is entered
2h = SHUTDOWN mode is entered
3h = Reserved

2.6.24 FCC Register (Offset = 1150h) [Reset = X]

FCC is shown in Figure 2-35 and described in Table 2-45.

Return to the Table 2-20.

Frequency clock counter (FCC) count

Figure 2-35 FCC Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-XR-0h
Table 2-45 FCC Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDRX
21-0DATAR0hFrequency clock counter (FCC) count value.

2.6.25 SYSOSCTRIMUSER Register (Offset = 1170h) [Reset = X]

SYSOSCTRIMUSER is shown in Figure 2-36 and described in Table 2-46.

Return to the Table 2-20.

SYSOSC user-specified trim

Figure 2-36 SYSOSCTRIMUSER Register
3130292827262524
RESERVEDRDIV
R/W-XR/W-0h
2322212019181716
RDIVRESFINE
R/W-0hR/W-0h
15141312111098
RESERVEDRESCOARSE
R/W-XR/W-0h
76543210
RESERVEDCAPRESERVEDFREQ
R/W-XR/W-0hR/W-XR/W-0h
Table 2-46 SYSOSCTRIMUSER Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-20RDIVR/W0hRDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency.
19-16RESFINER/W0hRESFINE specifies the resister fine trim. This value changes with the target frequency.
15-14RESERVEDR/WX
13-8RESCOARSER/W0hRESCOARSE specifies the resister coarse trim. This value changes with the target frequency.
7RESERVEDR/WX
6-4CAPR/W0hCAP specifies the SYSOSC capacitor trim. This value changes with the target frequency.
3-2RESERVEDR/WX
1-0FREQR/W0hFREQ specifies the target user-trimmed frequency for SYSOSC.
0h = Reserved
1h = 16MHz user frequency
2h = 24MHz user frequency
3h = Reserved

2.6.26 SRAMBOUNDARY Register (Offset = 1178h) [Reset = X]

SRAMBOUNDARY is shown in Figure 2-37 and described in Table 2-47.

Return to the Table 2-20.

SRAM Write Boundary

Figure 2-37 SRAMBOUNDARY Register
313029282726252423222120191817161514131211109876543210
RESERVEDADDRRESERVED
R/W-XR/W-0hR/W-X
Table 2-47 SRAMBOUNDARY Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-5ADDRR/W0hSRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size.
4-0RESERVEDR/WX

2.6.27 SYSTEMCFG Register (Offset = 1180h) [Reset = X]

SYSTEMCFG is shown in Figure 2-38 and described in Table 2-48.

Return to the Table 2-20.

System configuration

Figure 2-38 SYSTEMCFG Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDFLASHECCRSTDISWWDTLP1RSTDISWWDTLP0RSTDIS
R/W-XR/W-1hR/W-1hR/W-0h
Table 2-48 SYSTEMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0
1Bh = Issue write
23-3RESERVEDR/WX
2FLASHECCRSTDISR/W1hFLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI.
0h = Flash ECC DED will trigger a SYSRST
1h = Flash ECC DED will trigger a NMI
1WWDTLP1RSTDISR/W1hWWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI.
0h = WWDTLP1 Error Event will trigger a SYSRST
1h = WWDTLP1 Error Event will trigger an NMI
0WWDTLP0RSTDISR/W0hWWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI.
0h = WWDTLP0 Error Event will trigger a BOOTRST
1h = WWDTLP0 Error Event will trigger an NMI

2.6.28 WRITELOCK Register (Offset = 1200h) [Reset = X]

WRITELOCK is shown in Figure 2-39 and described in Table 2-49.

Return to the Table 2-20.

SYSCTL register write lockout

Figure 2-39 WRITELOCK Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDACTIVE
R/W-XR/W-0h
Table 2-49 WRITELOCK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/WX
0ACTIVER/W0hACTIVE controls whether critical SYSCTL registers are write protected or not.
0h = Allow writes to lockable registers
1h = Disallow writes to lockable registers

2.6.29 CLKSTATUS Register (Offset = 1204h) [Reset = X]

CLKSTATUS is shown in Figure 2-40 and described in Table 2-50.

Return to the Table 2-20.

Clock module (CKM) status

Figure 2-40 CLKSTATUS Register
3130292827262524
ANACLKERROPAMPCLKERRSYSPLLBLKUPDHFCLKBLKUPDRESERVEDFCCDONEFCLMODE
R-0hR-0hR-0hR-0hR-XR-0hR-0h
2322212019181716
LFCLKFAILRESERVEDHSCLKGOODHSCLKDEADRESERVEDCURMCLKSELCURHSCLKSEL
R-0hR-XR-0hR-0hR-XR-0hR-0h
15141312111098
RESERVEDSYSPLLOFFHFCLKOFFHSCLKSOFFLFOSCGOODLFXTGOODSYSPLLGOODHFCLKGOOD
R-XR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
LFCLKMUXRESERVEDHSCLKMUXRESERVEDSYSOSCFREQ
R-0hR-XR-0hR-XR-0h
Table 2-50 CLKSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31ANACLKERRR0hANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected.
0h = No analog clock errors detected
1h = Analog clock error detected
30OPAMPCLKERRR0hOPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected.
0h = No OPA clock generation errors detected
1h = OPA clock generation error detected
29SYSPLLBLKUPDR0hSYSPLLBLKUPD indicates when writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked.
0h = writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are allowed
1h = writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked
28HFCLKBLKUPDR0hHFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked.
0h = Writes to HFCLKCLKCFG are allowed
1h = Writes to HFCLKCLKCFG are blocked
27-26RESERVEDRX
25FCCDONER0hFCCDONE indicates when a frequency clock counter capture is complete.
0h = FCC capture is not done
1h = FCC capture is done
24FCLMODER0hFCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled.
0h = SYSOSC FCL is disabled
1h = SYSOSC FCL is enabled
23LFCLKFAILR0hLFCLKFAIL indicates when the continuous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure.
0h = No LFCLK fault detected
1h = LFCLK stuck fault detected
22RESERVEDRX
21HSCLKGOODR0hHSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully.
0h = The HSCLK source did not start correctly
1h = The HSCLK source started correctly
20HSCLKDEADR0hHSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully.
0h = The HSCLK source was not started or started correctly
1h = The HSCLK source did not start correctly
19-18RESERVEDRX
17CURMCLKSELR0hCURMCLKSEL indicates if MCLK is currently sourced from LFCLK.
0h = MCLK is not sourced from LFCLK
1h = MCLK is sourced from LFCLK
16CURHSCLKSELR0hCURHSCLKSEL indicates the current clock source for HSCLK.
0h = HSCLK is currently sourced from the SYSPLL
1h = HSCLK is currently sourced from the HFCLK
15RESERVEDRX
14SYSPLLOFFR0hSYSPLLOFF indicates if the SYSPLL is disabled or was dead at startup. When the SYSPLL is started, SYSPLLOFF is cleared by hardware. Following startup of the SYSPLL, if the SYSPLL startup monitor determines that the SYSPLL was not started correctly, SYSPLLOFF is set.
0h = SYSPLL started correctly and is enabled
1h = SYSPLL is disabled or was dead startup
13HFCLKOFFR0hHFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started, HFCLKOFF is cleared by hardware. Following startup of the HFCLK, if the HFCLK startup monitor determines that the HFCLK was not started correctly, HFCLKOFF is set.
0h = HFCLK started correctly and is enabled
1h = HFCLK is disabled or was dead at startup
12HSCLKSOFFR0hHSCLKSOFF is set when the high speed clock sources (SYSPLL, HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF.
0h = SYSPLL, HFCLK, or both were started correctly and remain enabled
1h = SYSPLL and HFCLK are both either off or dead
11LFOSCGOODR0hLFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use.
0h = LFOSC is not ready
1h = LFOSC is ready
10LFXTGOODR0hLFXTGOOD indicates if the LFXT started correctly. When the LFXT is started, LFXTGOOD is cleared by hardware. After the startup settling time has expired, the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set, else it is left cleared.
0h = LFXT did not start correctly
1h = LFXT started correctly
9SYSPLLGOODR0hSYSPLLGOOD indicates if the SYSPLL started correctly. When the SYSPLL is started, SYSPLLGOOD is cleared by hardware. After the startup settling time has expired, the SYSPLL status is tested. If the SYSPLL started successfully the SYSPLLGOOD bit is set, else it is left cleared.
0h = SYSPLL did not start correctly
1h = SYSPLL started correctly
8HFCLKGOODR0hHFCLKGOOD indicates that the HFCLK started correctly. When the HFXT is started or HFCLK_IN is selected as the HFCLK source, this bit will be set by hardware if a valid HFCLK is detected, and cleared if HFCLK is not operating within the expected range.
0h = HFCLK did not start correctly
1h = HFCLK started correctly
7-6LFCLKMUXR0hLFCLKMUX indicates if LFCLK is sourced from the internal LFOSC, the low frequency crystal (LFXT), or the LFCLK_IN digital clock input.
0h = LFCLK is sourced from the internal LFOSC
1h = LFCLK is sourced from the LFXT (crystal)
2h = LFCLK is sourced from LFCLK_IN (external digital clock input)
5RESERVEDRX
4HSCLKMUXR0hHSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK).
0h = MCLK is not sourced from HSCLK
1h = MCLK is sourced from HSCLK
3-2RESERVEDRX
1-0SYSOSCFREQR0hSYSOSCFREQ indicates the current SYSOSC operating frequency.
0h = SYSOSC is at base frequency (32MHz)
1h = SYSOSC is at low frequency (4MHz)
2h = SYSOSC is at the user-trimmed frequency (16 or 24MHz)
3h = Reserved

2.6.30 SYSSTATUS Register (Offset = 1208h) [Reset = X]

SYSSTATUS is shown in Figure 2-41 and described in Table 2-51.

Return to the Table 2-20.

System status information

Figure 2-41 SYSSTATUS Register
3130292827262524
REBOOTATTEMPTSRESERVED
R-0hR-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDSHDNIOLOCKSWDCFGDISEXTRSTPINDISRESERVEDMCAN0READY
R-XR-0hR-0hR-0hR-XR-0h
76543210
RESERVEDPMUIREFGOODANACPUMPGOODBORLVLBORCURTHRESHOLDFLASHSECFLASHDED
R-XR-0hR-0hR-0hR-0hR-0hR-0h
Table 2-51 SYSSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-30REBOOTATTEMPTSR0hREBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts.
29-15RESERVEDRX
14SHDNIOLOCKR0hSHDNIOLOCK indicates when IO is locked due to SHUTDOWN
0h = IO IS NOT Locked due to SHUTDOWN
1h = IO IS Locked due to SHUTDOWN
13SWDCFGDISR0hSWDCFGDIS indicates when user has disabled the use of SWD Port
0h = SWD Port Enabled
1h = SWD Port Disabled
12EXTRSTPINDISR0hEXTRSTPINDIS indicates when user has disabled the use of external reset pin
0h = External Reset Pin Enabled
1h = External Reset Pin Disabled
11-9RESERVEDRX
8MCAN0READYR0hMCAN0READY indicates when the MCAN0 peripheral is ready.
0h = MCAN0 is not ready
1h = MCAN0 is ready
7RESERVEDRX
6PMUIREFGOODR0hPMUIREFGOOD is set by hardware when the PMU current reference is ready.
0h = IREF is not ready
1h = IREF is ready
5ANACPUMPGOODR0hANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready.
0h = VBOOST is not ready
1h = VBOOST is ready
4BORLVLR0hBORLVL indicates if a BOR event occurred and the BOR threshold was switched to BOR0 by hardware.
0h = No BOR violation occurred
1h = A BOR violation occurred and the BOR threshold was switched to BOR0
3-2BORCURTHRESHOLDR0hBORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration.
0h = Default minimum threshold; a BOR0- violation triggers a BOR
1h = A BOR1- violation generates a BORLVL interrupt
2h = A BOR2- violation generates a BORLVL interrupt
3h = A BOR3- violation generates a BORLVL interrupt
1FLASHSECR0hFLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC).
0h = No flash ECC single bit error detected
1h = Flash ECC single bit error was detected and corrected
0FLASHDEDR0hFLASHDED indicates if a flash ECC double bit error was detected (DED).
0h = No flash ECC double bit error detected
1h = Flash ECC double bit error detected

2.6.31 DEDERRADDR Register (Offset = 120Ch) [Reset = 00000000h]

DEDERRADDR is shown in Figure 2-42 and described in Table 2-52.

Return to the Table 2-20.

Memory DED Address

Figure 2-42 DEDERRADDR Register
313029282726252423222120191817161514131211109876543210
ADDR
R-0h
Table 2-52 DEDERRADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR0hAddress of MEMORY DED Error.

2.6.32 RSTCAUSE Register (Offset = 1220h) [Reset = X]

RSTCAUSE is shown in Figure 2-43 and described in Table 2-53.

Return to the Table 2-20.

Reset cause

Figure 2-43 RSTCAUSE Register
313029282726252423222120191817161514131211109876543210
RESERVEDID
R-XRC-0h
Table 2-53 RSTCAUSE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDRX
4-0IDRC0hID is a read-to-clear field which indicates the lowest level reset cause since the last read.
0h = No reset since last read
1h = POR- violation, SHUTDNSTOREx or PMU trim parity fault
2h = NRST triggered POR (&gt;1s hold)
3h = Software triggered POR
4h = BOR0- violation
5h = SHUTDOWN mode exit
8h = Non-PMU trim parity fault
9h = Fatal clock failure
Ah = Software triggered BOOTRST
Ch = NRST triggered BOOTRST (<1s hold)
10h = BSL exit
11h = BSL entry
12h = WWDT0 violation
13h = WWDT1 violation
14h = Flash uncorrectable ECC error
15h = CPULOCK violation
1Ah = Debug triggered SYSRST
1Bh = Software triggered SYSRST
1Ch = Debug triggered CPURST
1Dh = Software triggered CPURST

2.6.33 RESETLEVEL Register (Offset = 1300h) [Reset = X]

RESETLEVEL is shown in Figure 2-44 and described in Table 2-54.

Return to the Table 2-20.

Reset level for application-triggered reset command

Figure 2-44 RESETLEVEL Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDLEVEL
R/W-XR/W-0h
Table 2-54 RESETLEVEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/WX
2-0LEVELR/W0hLEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.
0h = Issue a SYSRST (CPU plus peripherals only)
1h = Issue a BOOTRST (CPU, peripherals, and boot configuration routine)
2h = Issue a SYSRST and enter the boot strap loader (BSL)
3h = Issue a power-on reset (POR)
4h = Issue a SYSRST and exit the boot strap loader (BSL)

2.6.34 RESETCMD Register (Offset = 1304h) [Reset = X]

RESETCMD is shown in Figure 2-45 and described in Table 2-55.

Return to the Table 2-20.

Execute an application-triggered reset command

Figure 2-45 RESETCMD Register
31302928272625242322212019181716
KEYRESERVED
W-0hW-X
1514131211109876543210
RESERVEDGO
W-XW-0h
Table 2-55 RESETCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of E4h (228) must be written to KEY together with GO to trigger the reset.
E4h = Issue reset
23-1RESERVEDWX
0GOW0hExecute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.
1h = Issue reset

2.6.35 BORTHRESHOLD Register (Offset = 1308h) [Reset = X]

BORTHRESHOLD is shown in Figure 2-46 and described in Table 2-56.

Return to the Table 2-20.

BOR threshold selection

Figure 2-46 BORTHRESHOLD Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDLEVEL
R/W-XR/W-0h
Table 2-56 BORTHRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/WX
1-0LEVELR/W0hLEVEL specifies the desired BOR threshold and BOR mode.
0h = Default minimum threshold; a BOR0- violation triggers a BOR
1h = A BOR1- violation generates a BORLVL interrupt
2h = A BOR2- violation generates a BORLVL interrupt
3h = A BOR3- violation generates a BORLVL interrupt

2.6.36 BORCLRCMD Register (Offset = 130Ch) [Reset = X]

BORCLRCMD is shown in Figure 2-47 and described in Table 2-57.

Return to the Table 2-20.

Set the BOR threshold

Figure 2-47 BORCLRCMD Register
31302928272625242322212019181716
KEYRESERVED
W-0hW-X
1514131211109876543210
RESERVEDGO
W-XW-0h
Table 2-57 BORCLRCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change.
C7h = Issue clear
23-1RESERVEDWX
0GOW0hGO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register.
1h = Issue clear

2.6.37 SYSOSCFCLCTL Register (Offset = 1310h) [Reset = X]

SYSOSCFCLCTL is shown in Figure 2-48 and described in Table 2-58.

Return to the Table 2-20.

SYSOSC frequency correction loop (FCL) ROSC enable

Figure 2-48 SYSOSCFCLCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDSETUSEEXRESSETUSEFCL
W-XW-0hW-0h
Table 2-58 SYSOSCFCLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.
2Ah = Issue Command
23-2RESERVEDWX
1SETUSEEXRESW0hSet SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST.
1h = Enable the SYSOSC external Resistor
0SETUSEFCLW0hSet SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST.
1h = Enable the SYSOSC FCL

2.6.38 LFXTCTL Register (Offset = 1314h) [Reset = X]

LFXTCTL is shown in Figure 2-49 and described in Table 2-59.

Return to the Table 2-20.

LFXT and LFCLK control

Figure 2-49 LFXTCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDSETUSELFXTSTARTLFXT
W-XW-0hW-0h
Table 2-59 LFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit.
91h = Issue command
23-2RESERVEDWX
1SETUSELFXTW0hSet SETUSELFXT to switch LFCLK to LFXT. Once set, SETUSELFXT remains set until the next BOOTRST.
0h = 0
1h = Use LFXT as the LFCLK source
0STARTLFXTW0hSet STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set, STARTLFXT remains set until the next BOOTRST.
0h = LFXT not started
1h = Start LFXT

2.6.39 EXLFCTL Register (Offset = 1318h) [Reset = X]

EXLFCTL is shown in Figure 2-50 and described in Table 2-60.

Return to the Table 2-20.

LFCLK_IN and LFCLK control

Figure 2-50 EXLFCTL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDSETUSEEXLF
W-XW-0h
Table 2-60 EXLFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 36h (54) must be written to KEY together with SETUSEEXLF to set SETUSEEXLF.
36h = Issue command
23-1RESERVEDWX
0SETUSEEXLFW0hSet SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set, SETUSEEXLF remains set until the next BOOTRST.
1h = Use LFCLK_IN as the LFCLK source

2.6.40 SHDNIOREL Register (Offset = 131Ch) [Reset = X]

SHDNIOREL is shown in Figure 2-51 and described in Table 2-61.

Return to the Table 2-20.

SHUTDOWN IO release control

Figure 2-51 SHDNIOREL Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDRELEASE
W-XW-0h
Table 2-61 SHDNIOREL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 91h must be written to KEY together with RELEASE to set RELEASE.
91h = Issue command
23-1RESERVEDWX
0RELEASEW0hSet RELEASE to release the IO after a SHUTDOWN mode exit.
1h = Release IO

2.6.41 EXRSTPIN Register (Offset = 1320h) [Reset = X]

EXRSTPIN is shown in Figure 2-52 and described in Table 2-62.

Return to the Table 2-20.

Disable the reset function of the NRST pin

Figure 2-52 EXRSTPIN Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDDISABLE
W-XW-0h
Table 2-62 EXRSTPIN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 1Eh must be written together with DISABLE to disable the reset function.
1Eh = Issue command
23-1RESERVEDWX
0DISABLEW0hSet DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.
0h = Reset function of NRST pin is enabled
1h = Reset function of NRST pin is disabled

2.6.42 SYSSTATUSCLR Register (Offset = 1324h) [Reset = X]

SYSSTATUSCLR is shown in Figure 2-53 and described in Table 2-63.

Return to the Table 2-20.

Clear sticky bits of SYSSTATUS

Figure 2-53 SYSSTATUSCLR Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDALLECC
W-XW-0h
Table 2-63 SYSSTATUSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value CEh (206) must be written to KEY together with ALLECC to clear the ECC state.
CEh = Issue command
23-1RESERVEDWX
0ALLECCW0hSet ALLECC to clear all ECC related SYSSTATUS indicators.
1h = Clear ECC error state

2.6.43 SWDCFG Register (Offset = 1328h) [Reset = X]

SWDCFG is shown in Figure 2-54 and described in Table 2-64.

Return to the Table 2-20.

Disable the SWD function on the SWD pins

Figure 2-54 SWDCFG Register
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-X
15141312111098
RESERVED
W-X
76543210
RESERVEDDISABLE
W-XW-0h
Table 2-64 SWDCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions.
62h = Issue command
23-1RESERVEDWX
0DISABLEW0hSet DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO.
1h = Disable SWD function on SWD pins

2.6.44 FCCCMD Register (Offset = 132Ch) [Reset = X]

FCCCMD is shown in Figure 2-55 and described in Table 2-65.

Return to the Table 2-20.

Frequency clock counter start capture

Figure 2-55 FCCCMD Register
31302928272625242322212019181716
KEYRESERVED
W-0hW-X
1514131211109876543210
RESERVEDGO
W-XW-0h
Table 2-65 FCCCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 0Eh (14) must be written with GO to start a capture.
0Eh = Issue command
23-1RESERVEDWX
0GOW0hSet GO to start a capture with the frequency clock counter (FCC).
1h = 1

2.6.45 PMUOPAMP Register (Offset = 1380h) [Reset = X]

PMUOPAMP is shown in Figure 2-56 and described in Table 2-66.

Return to the Table 2-20.

GPAMP control

Figure 2-56 PMUOPAMP Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDCHOPCLKMODECHOPCLKFREQ
R/W-XR/W-0hR/W-0h
76543210
RESERVEDOUTENABLERRINSELPCHENABLEENABLE
R/W-XR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 2-66 PMUOPAMP Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR/WX
11-10CHOPCLKMODER/W0hCHOPCLKMODE selects the GPAMP chopping mode.
0h = Chopping disabled
1h = Normal chopping
2h = ADC Assisted chopping
3h = Reserved
9-8CHOPCLKFREQR/W0hCHOPCLKFREQ selects the GPAMP chopping clock frequency
0h = 16kHz
1h = 8kHz
2h = 4kHz
3h = 2kHz
7RESERVEDR/WX
6OUTENABLER/W0hSet OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin
0h = GPAMP_OUT signal is not connected to the GPAMP_OUT pin
1h = GPAMP_OUT signal is connected to the GPAMP_OUT pin
5-4RRIR/W0hRRI selects the rail-to-rail input mode.
0h = PMOS input pairs
1h = NMOS input pairs
2h = Rail-to-rail mode
3h = Rail-to-rail mode
3-2NSELR/W0hNSEL selects the GPAMP negative channel input.
0h = GPAMP_OUT pin connected to negative channel
1h = GPAMP_IN- pin connected to negative channel
2h = GPAMP_OUT signal connected to negative channel
3h = No channel selected
1PCHENABLER/W0hSet PCHENABLE to enable the positive channel input.
0h = Positive channel disabled
1h = GPAMP_IN+ connected to positive channel
0ENABLER/W0hSet ENABLE to turn on the GPAMP.
0h = GPAMP is disabled
1h = GPAMP is enabled

2.6.46 SHUTDNSTORE0 Register (Offset = 1400h) [Reset = X]

SHUTDNSTORE0 is shown in Figure 2-57 and described in Table 2-67.

Return to the Table 2-20.

Shutdown storage memory (byte 0)

Figure 2-57 SHUTDNSTORE0 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
DATA
R/W-0h
Table 2-67 SHUTDNSTORE0 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
9PARITYERRR0hParity error for SHUTDNSTORE0
8PARITYR/W0hParity for SHUTDNSTORE0
7-0DATAR/W0hShutdown storage byte 0

2.6.47 SHUTDNSTORE1 Register (Offset = 1404h) [Reset = X]

SHUTDNSTORE1 is shown in Figure 2-58 and described in Table 2-68.

Return to the Table 2-20.

Shutdown storage memory (byte 1)

Figure 2-58 SHUTDNSTORE1 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
DATA
R/W-0h
Table 2-68 SHUTDNSTORE1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
7-0DATAR/W0hShutdown storage byte 1

2.6.48 SHUTDNSTORE2 Register (Offset = 1408h) [Reset = X]

SHUTDNSTORE2 is shown in Figure 2-59 and described in Table 2-69.

Return to the Table 2-20.

Shutdown storage memory (byte 2)

Figure 2-59 SHUTDNSTORE2 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
DATA
R/W-0h
Table 2-69 SHUTDNSTORE2 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
7-0DATAR/W0hShutdown storage byte 2

2.6.49 SHUTDNSTORE3 Register (Offset = 140Ch) [Reset = X]

SHUTDNSTORE3 is shown in Figure 2-60 and described in Table 2-70.

Return to the Table 2-20.

Shutdown storage memory (byte 3)

Figure 2-60 SHUTDNSTORE3 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
DATA
R/W-0h
Table 2-70 SHUTDNSTORE3 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
7-0DATAR/W0hShutdown storage byte 3