SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 4-8 lists the memory-mapped registers for the DMA registers. All register offset addresses not listed in Table 4-8 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
400h | FSUB_0 | Subscriber Port 0 | Go | |
404h | FSUB_1 | Subscriber Port 1 | Go | |
444h | FPUB_1 | Publisher Port 0 | Go | |
1018h | PDBGCTL | Peripheral Debug Control | Go | |
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
1050h | IIDX | Interrupt index | GEN_EVENT | Go |
1058h | IMASK | Interrupt mask | GEN_EVENT | Go |
1060h | RIS | Raw interrupt status | GEN_EVENT | Go |
1068h | MIS | Masked interrupt status | GEN_EVENT | Go |
1070h | ISET | Interrupt set | GEN_EVENT | Go |
1078h | ICLR | Interrupt clear | GEN_EVENT | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10FCh | DESC | Module Description | Go | |
1100h | DMAPRIO | DMA Channel Priority Control | Go | |
1110h + formula | DMATCTL[j] | DMA Trigger Select | Go | |
1200h + formula | DMACTL[j] | DMA Channel Control | Go | |
1204h + formula | DMASA[j] | DMA Channel Source Address | Go | |
1208h + formula | DMADA[j] | DMA Channel Destination Address | Go | |
120Ch + formula | DMASZ[j] | DMA Channel Size | Go |
Complex bit access types are encoded to fit into small table cells. Table 4-9 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
FSUB_0 is shown in Figure 4-4 and described in Table 4-10.
Return to the Summary Table.
Subscriber port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | CHANID | R/W | 0h | 0 = disconnected. 1-255 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected FFh = Consult your device data sheet as the actual allowed maximum may be less than 255. |
FSUB_1 is shown in Figure 4-5 and described in Table 4-11.
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Subscriber port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | CHANID | R/W | 0h | 0 = disconnected. 1-255 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected FFh = Consult your device data sheet as the actual allowed maximum may be less than 255. |
FPUB_1 is shown in Figure 4-6 and described in Table 4-12.
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Publisher port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | CHANID | R/W | 0h | 0 = disconnected. 1-255 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected FFh = Consult your device data sheet as the actual allowed maximum may be less than 255. |
PDBGCTL is shown in Figure 4-7 and described in Table 4-13.
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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W- | R/W-1h | R/W-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | SOFT | R/W | 1h | Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption |
0 | FREE | R/W | 1h | Free run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 1h = The peripheral ignores the state of the Core Halted input |
IIDX is shown in Figure 4-8 and described in Table 4-14.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, . . . IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS [RIS] and MIS [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
00h = No bit is set means there is no pending interrupt request 01h = DMA Channel 0 size counter reached zero (DMASZ=0). 02h = DMA Channel 1 size counter reached zero (DMASZ=0). 03h = DMA Channel 2 size counter reached zero (DMASZ=0). 04h = DMA Channel 3 size counter reached zero (DMASZ=0). 05h = DMA Channel 4 size counter reached zero (DMASZ=0). 06h = DMA Channel 5 size counter reached zero (DMASZ=0). 07h = DMA Channel 6 size counter reached zero (DMASZ=0). 08h = DMA Channel 7 size counter reached zero (DMASZ=0). 09h = DMA Channel 8 size counter reached zero (DMASZ=0). 0Ah = DMA Channel 9 size counter reached zero (DMASZ=0). 0Bh = DMA Channel 10 size counter reached zero (DMASZ=0). 0Ch = DMA Channel 11 size counter reached zero (DMASZ=0). 0Dh = DMA Channel 12 size counter reached zero (DMASZ=0). 0Eh = DMA Channel 13 size counter reached zero (DMASZ=0). 0Fh = DMA Channel 14 size counter reached zero (DMASZ=0). 10h = DMA Channel 15 size counter reached zero (DMASZ=0). 11h = PRE-IRQ event for DMA Channel 0. 12h = PRE-IRQ event for DMA Channel 1. 13h = PRE-IRQ event for DMA Channel 2. 14h = PRE-IRQ event for DMA Channel 3. 15h = PRE-IRQ event for DMA Channel 4. 16h = PRE-IRQ event for DMA Channel 5. 17h = PRE-IRQ event for DMA Channel 6. 18h = PRE-IRQ event for DMA Channel 7. 19h = DMA address error, SRC address not reachable. 1Ah = DMA data error, SRC data might be corrupted (PAR or ECC error). |
IMASK is shown in Figure 4-9 and described in Table 4-15.
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Interrupt Mask. If a bit is set, then the corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX [IIDX], as well as MIS [MIS].
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | 0h | |
25 | DATAERR | R/W | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | R/W | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | R/W | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | R/W | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | R/W | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | R/W | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | R/W | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | R/W | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | R/W | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | R/W | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | R/W | 0h | DMA Channel 15 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
14 | DMACH14 | R/W | 0h | DMA Channel 14 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
13 | DMACH13 | R/W | 0h | DMA Channel 13 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
12 | DMACH12 | R/W | 0h | DMA Channel 12 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
11 | DMACH11 | R/W | 0h | DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
10 | DMACH10 | R/W | 0h | DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
9 | DMACH9 | R/W | 0h | DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
8 | DMACH8 | R/W | 0h | DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
7 | DMACH7 | R/W | 0h | DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
6 | DMACH6 | R/W | 0h | DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
5 | DMACH5 | R/W | 0h | DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
4 | DMACH4 | R/W | 0h | DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
3 | DMACH3 | R/W | 0h | DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
2 | DMACH2 | R/W | 0h | DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
1 | DMACH1 | R/W | 0h | DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
0 | DMACH0 | R/W | 0h | DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
RIS is shown in Figure 4-10 and described in Table 4-16.
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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR [ICLR] register bit even if the corresponding IMASK [IMASK] bit is not enabled.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | |
25 | DATAERR | R | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | R | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | R | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | R | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | R | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | R | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | R | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | R | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | R | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | R | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | R | 0h | DMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
14 | DMACH14 | R | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
13 | DMACH13 | R | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
12 | DMACH12 | R | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
11 | DMACH11 | R | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
10 | DMACH10 | R | 0h | DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
9 | DMACH9 | R | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
8 | DMACH8 | R | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
7 | DMACH7 | R | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
6 | DMACH6 | R | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
5 | DMACH5 | R | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
4 | DMACH4 | R | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
3 | DMACH3 | R | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
2 | DMACH2 | R | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
1 | DMACH1 | R | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
0 | DMACH0 | R | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Figure 4-11 and described in Table 4-17.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK [IMASK] and RIS [RIS] registers.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | |
25 | DATAERR | R | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | R | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | R | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | R | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | R | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | R | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | R | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | R | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | R | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | R | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | R | 0h | DMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
14 | DMACH14 | R | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
13 | DMACH13 | R | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
12 | DMACH12 | R | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
11 | DMACH11 | R | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
10 | DMACH10 | R | 0h | DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
9 | DMACH9 | R | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
8 | DMACH8 | R | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
7 | DMACH7 | R | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
6 | DMACH6 | R | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
5 | DMACH5 | R | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
4 | DMACH4 | R | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
3 | DMACH3 | R | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
2 | DMACH2 | R | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
1 | DMACH1 | R | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
0 | DMACH0 | R | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
ISET is shown in Figure 4-12 and described in Table 4-18.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS [RIS] bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS [MIS] bit is also set.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
W-0h | W-0h | W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | W | 0h | |
25 | DATAERR | W | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | W | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | W | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | W | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | W | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | W | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | W | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | W | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | W | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | W | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
14 | DMACH14 | W | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
13 | DMACH13 | W | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
12 | DMACH12 | W | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
11 | DMACH11 | W | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
10 | DMACH10 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
9 | DMACH9 | W | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
8 | DMACH8 | W | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
7 | DMACH7 | W | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
6 | DMACH6 | W | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
5 | DMACH5 | W | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
4 | DMACH4 | W | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
3 | DMACH3 | W | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
2 | DMACH2 | W | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
1 | DMACH1 | W | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
0 | DMACH0 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
ICLR is shown in Figure 4-13 and described in Table 4-19.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
W-0h | W-0h | W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | W | 0h | |
25 | DATAERR | W | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | W | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | W | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | W | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | W | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | W | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | W | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | W | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | W | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | W | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | W | 0h | DMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
14 | DMACH14 | W | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
13 | DMACH13 | W | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
12 | DMACH12 | W | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
11 | DMACH11 | W | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
10 | DMACH10 | W | 0h | DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
9 | DMACH9 | W | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
8 | DMACH8 | W | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
7 | DMACH7 | W | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
6 | DMACH6 | W | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
5 | DMACH5 | W | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
4 | DMACH4 | W | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
3 | DMACH3 | W | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
2 | DMACH2 | W | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
1 | DMACH1 | W | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
0 | DMACH0 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
IIDX is shown in Figure 4-14 and described in Table 4-20.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, . . . IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS [RIS] and MIS [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
00h = No bit is set means there is no pending interrupt request 01h = DMA Channel 0 size counter reached zero (DMASZ=0). 02h = DMA Channel 1 size counter reached zero (DMASZ=0). 03h = DMA Channel 2 size counter reached zero (DMASZ=0). 04h = DMA Channel 3 size counter reached zero (DMASZ=0). 05h = DMA Channel 4 size counter reached zero (DMASZ=0). 06h = DMA Channel 5 size counter reached zero (DMASZ=0). 07h = DMA Channel 6 size counter reached zero (DMASZ=0). 08h = DMA Channel 7 size counter reached zero (DMASZ=0). 09h = DMA Channel 8 size counter reached zero (DMASZ=0). 0Ah = DMA Channel 9 size counter reached zero (DMASZ=0). 0Bh = DMA Channel 10 size counter reached zero (DMASZ=0). 0Ch = DMA Channel 11 size counter reached zero (DMASZ=0). 0Dh = DMA Channel 12 size counter reached zero (DMASZ=0). 0Eh = DMA Channel 13 size counter reached zero (DMASZ=0). 0Fh = DMA Channel 14 size counter reached zero (DMASZ=0). 10h = DMA Channel 15 size counter reached zero (DMASZ=0). 11h = PRE-IRQ event for DMA Channel 0. 12h = PRE-IRQ event for DMA Channel 1. 13h = PRE-IRQ event for DMA Channel 2. 14h = PRE-IRQ event for DMA Channel 3. 15h = PRE-IRQ event for DMA Channel 4. 16h = PRE-IRQ event for DMA Channel 5. 17h = PRE-IRQ event for DMA Channel 6. 18h = PRE-IRQ event for DMA Channel 7. 19h = DMA address error, SRC address not reachable. 1Ah = DMA data error, SRC data might be corrupted (PAR or ECC error). |
IMASK is shown in Figure 4-15 and described in Table 4-21.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then the corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX [IIDX], as well as MIS [MIS].
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | 0h | |
25 | DATAERR | R/W | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | R/W | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | R/W | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | R/W | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | R/W | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | R/W | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | R/W | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | R/W | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | R/W | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | R/W | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | R/W | 0h | DMA Channel 15 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
14 | DMACH14 | R/W | 0h | DMA Channel 14 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
13 | DMACH13 | R/W | 0h | DMA Channel 13 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
12 | DMACH12 | R/W | 0h | DMA Channel 12 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
11 | DMACH11 | R/W | 0h | DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
10 | DMACH10 | R/W | 0h | DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
9 | DMACH9 | R/W | 0h | DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
8 | DMACH8 | R/W | 0h | DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
7 | DMACH7 | R/W | 0h | DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
6 | DMACH6 | R/W | 0h | DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
5 | DMACH5 | R/W | 0h | DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
4 | DMACH4 | R/W | 0h | DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
3 | DMACH3 | R/W | 0h | DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
2 | DMACH2 | R/W | 0h | DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
1 | DMACH1 | R/W | 0h | DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
0 | DMACH0 | R/W | 0h | DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
RIS is shown in Figure 4-16 and described in Table 4-22.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR [ICLR] register bit even if the corresponding IMASK [IMASK] bit is not enabled.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | |
25 | DATAERR | R | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | R | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | R | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | R | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | R | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | R | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | R | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | R | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | R | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | R | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | R | 0h | DMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
14 | DMACH14 | R | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
13 | DMACH13 | R | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
12 | DMACH12 | R | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
11 | DMACH11 | R | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
10 | DMACH10 | R | 0h | DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
9 | DMACH9 | R | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
8 | DMACH8 | R | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
7 | DMACH7 | R | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
6 | DMACH6 | R | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
5 | DMACH5 | R | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
4 | DMACH4 | R | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
3 | DMACH3 | R | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
2 | DMACH2 | R | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
1 | DMACH1 | R | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
0 | DMACH0 | R | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Figure 4-17 and described in Table 4-23.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK [IMASK] and RIS [RIS] registers.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
R-0h | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | |
25 | DATAERR | R | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | R | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | R | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | R | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | R | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | R | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | R | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | R | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | R | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | R | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | R | 0h | DMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
14 | DMACH14 | R | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
13 | DMACH13 | R | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
12 | DMACH12 | R | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
11 | DMACH11 | R | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
10 | DMACH10 | R | 0h | DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
9 | DMACH9 | R | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
8 | DMACH8 | R | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
7 | DMACH7 | R | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
6 | DMACH6 | R | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
5 | DMACH5 | R | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
4 | DMACH4 | R | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
3 | DMACH3 | R | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
2 | DMACH2 | R | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
1 | DMACH1 | R | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
0 | DMACH0 | R | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Interrupt did not occur or is masked out 1h = Interrupt occurred |
ISET is shown in Figure 4-18 and described in Table 4-24.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS [RIS] bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS [MIS] bit is also set.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
W-0h | W-0h | W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | W | 0h | |
25 | DATAERR | W | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | W | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | W | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | W | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | W | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | W | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | W | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | W | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | W | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | W | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
14 | DMACH14 | W | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
13 | DMACH13 | W | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
12 | DMACH12 | W | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
11 | DMACH11 | W | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
10 | DMACH10 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
9 | DMACH9 | W | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
8 | DMACH8 | W | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
7 | DMACH7 | W | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
6 | DMACH6 | W | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
5 | DMACH5 | W | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
4 | DMACH4 | W | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
3 | DMACH3 | W | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
2 | DMACH2 | W | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
1 | DMACH1 | W | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
0 | DMACH0 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Set interrupt |
ICLR is shown in Figure 4-19 and described in Table 4-25.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
Note: The number of DMACH is device dependent. Please consult the data sheet of the specific device to map which channel number is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DATAERR | ADDRERR | |||||
W-0h | W-0h | W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PREIRQCH7 | PREIRQCH6 | PREIRQCH5 | PREIRQCH4 | PREIRQCH3 | PREIRQCH2 | PREIRQCH1 | PREIRQCH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMACH15 | DMACH14 | DMACH13 | DMACH12 | DMACH11 | DMACH10 | DMACH9 | DMACH8 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMACH7 | DMACH6 | DMACH5 | DMACH4 | DMACH3 | DMACH2 | DMACH1 | DMACH0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | W | 0h | |
25 | DATAERR | W | 0h | DMA data error, SRC data might be corrupted (PAR or ECC error).
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
24 | ADDRERR | W | 0h | DMA address error, SRC address not reachable.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
23 | PREIRQCH7 | W | 0h | Pre-IRQ for Channel 7. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
22 | PREIRQCH6 | W | 0h | Pre-IRQ for Channel 6. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
21 | PREIRQCH5 | W | 0h | Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
20 | PREIRQCH4 | W | 0h | Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
19 | PREIRQCH3 | W | 0h | Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
18 | PREIRQCH2 | W | 0h | Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
17 | PREIRQCH1 | W | 0h | Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
16 | PREIRQCH0 | W | 0h | Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.
0h = Clear interrupt mask bit 1h = Set interrupt mask bit |
15 | DMACH15 | W | 0h | DMA Channel 15 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
14 | DMACH14 | W | 0h | DMA Channel 14 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
13 | DMACH13 | W | 0h | DMA Channel 13 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
12 | DMACH12 | W | 0h | DMA Channel 12 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
11 | DMACH11 | W | 0h | DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
10 | DMACH10 | W | 0h | DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
9 | DMACH9 | W | 0h | DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
8 | DMACH8 | W | 0h | DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
7 | DMACH7 | W | 0h | DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
6 | DMACH6 | W | 0h | DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
5 | DMACH5 | W | 0h | DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
4 | DMACH4 | W | 0h | DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
3 | DMACH3 | W | 0h | DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
2 | DMACH2 | W | 0h | DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
1 | DMACH1 | W | 0h | DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
0 | DMACH0 | W | 0h | DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).
0h = Writing 0 has no effect 1h = Clear interrupt |
EVT_MODE is shown in Figure 4-20 and described in Table 4-26.
Return to the Summary Table.
Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT1_CFG | INT0_CFG | |||||
R/W- | R-2h | R-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-2 | EVT1_CFG | R | 2h | Event line mode select for event corresponding to generic event GEN_EVENT
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | INT0_CFG | R | 1h | Event line mode select for event corresponding to interrupt event CPU_INT
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
DESC is shown in Figure 4-21 and described in Table 4-27.
Return to the Summary Table.
This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-2511h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | RESERVED | MAJREV | MINREV | ||||||||||||
R-Fh | R- | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 2511h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value FFFFh = Highest possible value |
15-12 | FEATUREVER | R | Fh | Feature Set for the DMA: number of DMA channel minus one (for example 0->1ch, 2->3ch, 15->16ch). 0h = Smallest value (1 channel) Fh = Highest value (16 channel) |
11-8 | RESERVED | R | 0h | |
7-4 | MAJREV | R | 0h | Major rev of the IP
0h = Smallest value Fh = Highest possible value |
3-0 | MINREV | R | 0h | Minor rev of the IP
0h = Smallest value Fh = Highest possible value |
DMAPRIO is shown in Figure 4-22 and described in Table 4-28.
Return to the Summary Table.
DMA Channel Priority Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BURSTSZ | ||||||
R/W- | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ROUNDROBIN | ||||||
R/W- | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | 0h | |
17-16 | BURSTSZ | R/W | 0h | Define the burst size of a block transfer, before the priority is re-evaluated
0h = There is no burst size, the whole block transfer is completed on one transfer without interruption 1h = The burst size is 8, after 8 transfers the block transfer is interrupted and the priority is reevaluated 2h = The burst size is 16, after 16 transfers the block transfer is interrupted and the priority is reevaluated 3h = The burst size is 32, after 32 transfers the block transfer is interrupted and the priority is reevaluated |
15-1 | RESERVED | R/W | 0h | |
0 | ROUNDROBIN | R/W | 0h | Round robin. This bit enables the round-robin DMA channel priorities. 0h = Round robin priority disabled, DMA channel priority is fixed: DMA0-DMA1-DMA2-...-DMA16 1h = Round robin priority enabled, DMA channel priority changes with each transfer |
DMATCTL[j] is shown in Figure 4-23 and described in Table 4-29.
Return to the Summary Table.
DMA Trigger Control
Offset = 1110h + (j * 4h); where j = 0h to Fh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATINT | RESERVED | DMATSEL | |||||
R/W-0h | R/W- | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7 | DMATINT | R/W | 0h | DMA Trigger by Internal Channel
0h = DMATSEL will define external trigger select as transfer trigger. 1h = DMATSEL will define internal channel as transfer trigger select. 0-> Channel0-done, 1-> Channel1-done, ... |
6 | RESERVED | R/W | 0h | |
5-0 | DMATSEL | R/W | 0h | DMA Trigger Select Note: Reference the data sheet of the device to see the specific trigger mapping. 00h = Software trigger request 3Fh = Highest possible value |
DMACTL[j] is shown in Figure 4-24 and described in Table 4-30.
Return to the Summary Table.
DMA Channel Control
Offset = 1200h + (j * 10h); where j = 0h to Fh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMATM | RESERVED | DMAEM | ||||
R/W- | R/W-0h | R/W- | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DMADSTINCR | DMASRCINCR | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADSTWDTH | RESERVED | DMASRCWDTH | ||||
R/W- | R/W-0h | R/W- | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAPREIRQ | RESERVED | DMAEN | DMAREQ | |||
R/W- | R/W-0h | R/W- | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | |
29-28 | DMATM | R/W | 0h | DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the data sheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set. 0h = Single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated and the DMAEN is cleared. 1h = Block transfer. Each trigger transfers the complete block defined in DMASZ. After the transfer is complete an event can be generated and the DMAEN is cleared. 2h = Repeated single transfer. Each transfers requires a new trigger. When the DMASZ counts down to zero an event can be generated. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled. 3h = Repeated block transfer. Each trigger transfers the complete block defined in DMASZ. After the last transfer the DMASA, DMADA, DAMSZ registers are restored to its initial value and the DMAEN stays enabled. |
27-26 | RESERVED | R/W | 0h | |
25-24 | DMAEM | R/W | 0h | DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the data sheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0. 0h = Normal mode is related to transfers from SRC to DST 2h = Fill mode will copy the SA register content as data to DA 3h = Table mode will read an address and data value from SA and write the data to address |
23-20 | DMADSTINCR | R/W | 0h | DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definition in the DMADSTWDTH. For example an
increment of 1 (+1) on a WORD transfer will increment the DMADA by 4. 0h = Address is unchanged (+0) 2h = Decremented by 1 (-1 * DMADSTWDTH) 3h = Incremented by 1 (+1 * DMADSTWDTH) 8h = Stride size 2 (+2 * DMADSTWDTH) 9h = Stride size 3 (+3 * DMADSTWDTH) Ah = Stride size 4 (+4 * DMADSTWDTH) Bh = Stride size 5 (+5 * DMADSTWDTH) Ch = Stride size 6 (+6 * DMADSTWDTH) Dh = Stride size 7 (+7 * DMADSTWDTH) Eh = Stride size 8 (+8 * DMADSTWDTH) Fh = Stride size 9 (+9 * DMADSTWDTH) |
19-16 | DMASRCINCR | R/W | 0h | DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definition in the DMASRCWDTH. For example an increment of 1
(+1) on a WORD transfer will increment the DMASA by 4. 0h = Address is unchanged (+0) 2h = Decremented by 1 (-1 * DMASRCWDTH) 3h = Incremented by 1 (+1 * DMASRCWDTH) 8h = Stride size 2 (+2 * DMASRCWDTH) 9h = Stride size 3 (+3 * DMASRCWDTH) Ah = Stride size 4 (+4 * DMASRCWDTH) Bh = Stride size 5 (+5 * DMASRCWDTH) Ch = Stride size 6 (+6 * DMASRCWDTH) Dh = Stride size 7 (+7 * DMASRCWDTH) Eh = Stride size 8 (+8 * DMASRCWDTH) Fh = Stride size 9 (+9 * DMASRCWDTH) |
15-14 | RESERVED | R/W | 0h | |
13-12 | DMADSTWDTH | R/W | 0h | DMA destination width. This bit selects the destination as a byte, half word, word or long word.
0h = Destination data width is BYTE (8-bit) 1h = Destination data width is HALF-WORD (16-bit) 2h = Destination data width is WORD (32-bit) 3h = Destination data width is LONG-WORD (64-bit) |
11-10 | RESERVED | R/W | 0h | |
9-8 | DMASRCWDTH | R/W | 0h | DMA source width. This bit selects the source data width as a byte, half word, word or long word.
0h = Source data width is BYTE (8-bit) 1h = Source data width is HALF-WORD (16-bit) 2h = Source data width is WORD (32-bit) 3h = Source data width is LONG-WORD (64-bit) |
7 | RESERVED | R/W | 0h | |
6-4 | DMAPREIRQ | R/W | 0h | Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the data sheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0. 0h = Pre-IRQ event disabled. 1h = Issue Pre-IRQ event when DMASZ=1 2h = Issue Pre-IRQ event when DMASZ=2 3h = Issue Pre-IRQ event when DMASZ=4 4h = Issue Pre-IRQ event when DMASZ=8 5h = Issue Pre-IRQ event when DMASZ=32 6h = Issue Pre-IRQ event when DMASZ=64 7h = Issue Pre-IRQ event when DMASZ reached the half size point of the original transfer size |
3-2 | RESERVED | R/W | 0h | |
1 | DMAEN | R/W | 0h | DMA enable
0h = DMA channel disabled 1h = DMA channel enabled |
0 | DMAREQ | R/W | 0h | DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0h = Default read value 1h = DMA transfer request (start DMA) |
DMASA[j] is shown in Figure 4-25 and described in Table 4-31.
Return to the Summary Table.
DMA Channel Source Address
Offset = 1204h + (j * 10h); where j = 0h to Fh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR | R/W | 0h | DMA Channel Source Address
0h = Smallest value FFFFFFFFh = Highest possible value |
DMADA[j] is shown in Figure 4-26 and described in Table 4-32.
Return to the Summary Table.
DMA Channel Destination Address
Offset = 1208h + (j * 10h); where j = 0h to Fh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR | R/W | 0h | DMA Channel Destination Address
0h = Smallest value FFFFFFFFh = Highest possible value |
DMASZ[j] is shown in Figure 4-27 and described in Table 4-33.
Return to the Summary Table.
DMA Channel Size
Offset = 120Ch + (j * 10h); where j = 0h to Fh
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIZE | ||||||||||||||||||||||||||||||
R/W- | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | SIZE | R/W | 0h | DMA Channel Size in number of transfers
0h = Smallest value FFFFh = Highest possible value |