SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 14-7 lists the memory-mapped registers for the DAC12 registers. All register offset addresses not listed in Table 14-7 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
400h | FSUB_0 | Subscriber Port 0 | Go | |
444h | FPUB_1 | Publisher port 1 | Go | |
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
814h | STAT | Status Register | Go | |
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
1050h | IIDX | Interrupt index | GEN_EVENT | Go |
1058h | IMASK | Interrupt mask | GEN_EVENT | Go |
1060h | RIS | Raw interrupt status | GEN_EVENT | Go |
1068h | MIS | Masked interrupt status | GEN_EVENT | Go |
1070h | ISET | Interrupt set | GEN_EVENT | Go |
1078h | ICLR | Interrupt clear | GEN_EVENT | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10FCh | DESC | Module Description | Go | |
1100h | CTL0 | Control 0 | Go | |
1110h | CTL1 | Control 1 | Go | |
1120h | CTL2 | Control 2 | Go | |
1130h | CTL3 | Control 3 | Go | |
1140h | CALCTL | Calibration control | Go | |
1160h | CALDATA | Calibration data | Go | |
1200h | DATA0 | Data 0 | Go |
Complex bit access types are encoded to fit into small table cells. Table 14-8 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | R H |
Read Set or cleared by hardware |
Write Type | ||
K | K | Write protected by a key |
W | W | Write |
WK | W K |
Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
FSUB_0 is shown in Figure 14-8 and described in Table 14-9.
Return to the Summary Table.
Subscriber port 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W- | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W- | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. others = connected to channel_ID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
FPUB_1 is shown in Figure 14-9 and described in Table 14-10.
Return to the Summary Table.
Publisher port 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W- | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W- | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. others = connected to channel_ID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
PWREN is shown in Figure 14-10 and described in Table 14-11.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W- | K-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change 26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | K | 0h | Enable the power
KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 14-11 and described in Table 14-12.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W- | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register
KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral
KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 14-12 and described in Table 14-13.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
IIDX is shown in Figure 14-13 and described in Table 14-14.
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Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority
order is fixed: lower index equals higher priority. Alternatively, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared
as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are
indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3-0 | STAT | R | 0h | Interrupt index status 0h = No pending interrupt 2h = Module ready interrupt 9h = FIFO full interrupt Ah = FIFO one fourth empty interrupt Bh = FIFO half empty interrupt Ch = FIFO three fourth empty interrupt Dh = FIFO empty interrupt Eh = FIFO underrun interrupt Fh = DMA done interrupt |
IMASK is shown in Figure 14-14 and described in Table 14-15.
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Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | 0h | |
14 | DMADONEIFG | R/W | 0h | Masks DMADONEIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
13 | FIFOURUNIFG | R/W | 0h | Masks FIFOURUNIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
12 | FIFOEMPTYIFG | R/W | 0h | Masks FIFOEMPTYIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
11 | FIFO3B4IFG | R/W | 0h | Masks FIFO3B4IFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
10 | FIFO1B2IFG | R/W | 0h | Masks FIFO1B2IFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
9 | FIFO1B4IFG | R/W | 0h | Masks FIFO1B4IFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
8 | FIFOFULLIFG | R/W | 0h | Masks FIFOFULLIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
7-2 | RESERVED | R/W | 0h | |
1 | MODRDYIFG | R/W | 0h | Masks MODRDYIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
0 | RESERVED | R/W | 0h |
RIS is shown in Figure 14-15 and described in Table 14-16.
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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
R-0h | R-0h | R-0h | R-1h | R-1h | R-1h | R-1h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | |
14 | DMADONEIFG | R | 0h | Raw interrupt status for DMADONEIFG 0h = DMA done condition did not occur 1h = DMA done condition occurred |
13 | FIFOURUNIFG | R | 0h | Raw interrupt status for FIFOURUNIFG 0h = FIFO underrun condition did not occur 1h = FIFO underrun condition occurred |
12 | FIFOEMPTYIFG | R | 1h | Raw interrupt status for FIFOEMPTYIFG 0h = FIFO empty condition did not occur 1h = FIFO empty condition occurred |
11 | FIFO3B4IFG | R | 1h | Raw interrupt status for FIFO3B4IFG 0h = FIFO three fourth empty condition did not occur 1h = FIFO three fourth empty condition occurred |
10 | FIFO1B2IFG | R | 1h | Raw interrupt status for FIFO1B2IFG 0h = FIFO half empty condition did not occur 1h = FIFO half empty condition occurred |
9 | FIFO1B4IFG | R | 1h | Raw interrupt status for FIFO1B4IFG 0h = FIFO one fourth empty condition did not occur 1h = FIFO one fourth empty condition occurred |
8 | FIFOFULLIFG | R | 0h | Raw interrupt status for FIFOFULLIFG 0h = FIFO full condition did not occur 1h = FIFO full condition occurred |
7-2 | RESERVED | R | 0h | |
1 | MODRDYIFG | R | 0h | Raw interrupt status for MODRDYIFG 0h = DAC module ready event did not occur 1h = DAC module ready event occurred |
0 | RESERVED | R | 0h |
MIS is shown in Figure 14-16 and described in Table 14-17.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | |
14 | DMADONEIFG | R | 0h | Masked interrupt status for DMADONEIFG 0h = DMADONEIFG does not request an interrupt service routine 1h = DMADONEIFG requests an interrupt service routine |
13 | FIFOURUNIFG | R | 0h | Masked interrupt status for FIFOURUNIFG 0h = FIFOURUNIFG does not request an interrupt service routine 1h = FIFOURUNIFG requests an interrupt service routine |
12 | FIFOEMPTYIFG | R | 0h | Masked interrupt status for FIFOEMPTYIFG 0h = FIFOEMPTYIFG does not request an interrupt service routine 1h = FIFOEMPTYIFG requests an interrupt service routine |
11 | FIFO3B4IFG | R | 0h | Masked interrupt status for FIFO3B4IFG 0h = FIFO3B4IFG does not request an interrupt service routine 1h = FIFO3B4IFG requests an interrupt service routine |
10 | FIFO1B2IFG | R | 0h | Masked interrupt status for FIFO1B2IFG 0h = FIFO1B2IFG does not request an interrupt service routine 1h = FIFO1B2IFG requests an interrupt service routine |
9 | FIFO1B4IFG | R | 0h | Masked interrupt status for FIFO1B4IFG 0h = FIFO1B4IFG does not request an interrupt service routine 1h = FIFO1B4IFG requests an interrupt service routine |
8 | FIFOFULLIFG | R | 0h | Masked interrupt status for FIFOFULLIFG 0h = FIFOFULLIFG does not request an interrupt service routine 1h = FIFOFULLIFG requests an interrupt service routine |
7-2 | RESERVED | R | 0h | |
1 | MODRDYIFG | R | 0h | Masked interrupt status for MODRDYIFG 0h = MODRDYIFG does not request an interrupt service routine 1h = MODRDYIFG requests an interrupt service routine |
0 | RESERVED | R | 0h |
ISET is shown in Figure 14-17 and described in Table 14-18.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | W | 0h | |
14 | DMADONEIFG | W | 0h | Sets DMADONEIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to DMADONEIFG is set |
13 | FIFOURUNIFG | W | 0h | Sets FIFOURUNIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOURUNIFG is set |
12 | FIFOEMPTYIFG | W | 0h | Sets FIFOEMPTYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOEMPTYIFG is set |
11 | FIFO3B4IFG | W | 0h | Sets FIFO3B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO3B4IFG is set |
10 | FIFO1B2IFG | W | 0h | Sets FIFO1B2IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B2IFG is set |
9 | FIFO1B4IFG | W | 0h | Sets FIFO1B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B4IFG is set |
8 | FIFOFULLIFG | W | 0h | Sets FIFOFULLIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOFULLIFG is set |
7-2 | RESERVED | W | 0h | |
1 | MODRDYIFG | W | 0h | Sets MODRDYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to MODRDYIFG is set |
0 | RESERVED | W | 0h |
ICLR is shown in Figure 14-18 and described in Table 14-19.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | W | 0h | |
14 | DMADONEIFG | W | 0h | Clears DMADONEIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to DMADONEIFG is cleared |
13 | FIFOURUNIFG | W | 0h | Clears FIFOURUNIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOURUNIFG is cleared |
12 | FIFOEMPTYIFG | W | 0h | Clears FIFOEMPTYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOEMPTYIFG is cleared |
11 | FIFO3B4IFG | W | 0h | Clears FIFO3B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO3B4IFG is cleared |
10 | FIFO1B2IFG | W | 0h | Clears FIFO1B2IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B2IFG is cleared |
9 | FIFO1B4IFG | W | 0h | Clears FIFO1B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B4IFG is cleared |
8 | FIFOFULLIFG | W | 0h | Clears FIFOFULLIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOFULLIFG is cleared |
7-2 | RESERVED | W | 0h | |
1 | MODRDYIFG | W | 0h | Clears MODRDYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to MODRDYIFG is cleared |
0 | RESERVED | W | 0h |
IIDX is shown in Figure 14-19 and described in Table 14-20.
Return to the Summary Table.
Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority
order is fixed: lower index equals higher priority. Alternatively, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared
as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are
indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3-0 | STAT | R | 0h | Interrupt index status 0h = No pending interrupt 2h = Module ready interrupt 9h = FIFO full interrupt Ah = FIFO one fourth empty interrupt Bh = FIFO half empty interrupt Ch = FIFO three fourth empty interrupt Dh = FIFO empty interrupt Eh = FIFO underrun interrupt Fh = DMA done interrupt |
IMASK is shown in Figure 14-20 and described in Table 14-21.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | 0h | |
14 | DMADONEIFG | R/W | 0h | Masks DMADONEIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
13 | FIFOURUNIFG | R/W | 0h | Masks FIFOURUNIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
12 | FIFOEMPTYIFG | R/W | 0h | Masks FIFOEMPTYIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
11 | FIFO3B4IFG | R/W | 0h | Masks FIFO3B4IFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
10 | FIFO1B2IFG | R/W | 0h | Masks FIFO1B2IFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
9 | FIFO1B4IFG | R/W | 0h | Masks FIFO1B4IFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
8 | FIFOFULLIFG | R/W | 0h | Masks FIFOFULLIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
7-2 | RESERVED | R/W | 0h | |
1 | MODRDYIFG | R/W | 0h | Masks MODRDYIFG 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set |
0 | RESERVED | R/W | 0h |
RIS is shown in Figure 14-21 and described in Table 14-22.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
R-0h | R-0h | R-0h | R-1h | R-1h | R-1h | R-1h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | |
14 | DMADONEIFG | R | 0h | Raw interrupt status for DMADONEIFG 0h = DMA done condition did not occur 1h = DMA done condition occurred |
13 | FIFOURUNIFG | R | 0h | Raw interrupt status for FIFOURUNIFG 0h = FIFO underrun condition did not occur 1h = FIFO underrun condition occurred |
12 | FIFOEMPTYIFG | R | 1h | Raw interrupt status for FIFOEMPTYIFG 0h = FIFO empty condition did not occur 1h = FIFO empty condition occurred |
11 | FIFO3B4IFG | R | 1h | Raw interrupt status for FIFO3B4IFG 0h = FIFO three fourth empty condition did not occur 1h = FIFO three fourth empty condition occurred |
10 | FIFO1B2IFG | R | 1h | Raw interrupt status for FIFO1B2IFG 0h = FIFO half empty condition did not occur 1h = FIFO half empty condition occurred |
9 | FIFO1B4IFG | R | 1h | Raw interrupt status for FIFO1B4IFG 0h = FIFO one fourth empty condition did not occur 1h = FIFO one fourth empty condition occurred |
8 | FIFOFULLIFG | R | 0h | Raw interrupt status for FIFOFULLIFG 0h = FIFO full condition did not occur 1h = FIFO full condition occurred |
7-2 | RESERVED | R | 0h | |
1 | MODRDYIFG | R | 0h | Raw interrupt status for MODRDYIFG 0h = DAC module ready event did not occur 1h = DAC module ready event occurred |
0 | RESERVED | R | 0h |
MIS is shown in Figure 14-22 and described in Table 14-23.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | |
14 | DMADONEIFG | R | 0h | Masked interrupt status for DMADONEIFG 0h = DMADONEIFG does not request an interrupt service routine 1h = DMADONEIFG requests an interrupt service routine |
13 | FIFOURUNIFG | R | 0h | Masked interrupt status for FIFOURUNIFG 0h = FIFOURUNIFG does not request an interrupt service routine 1h = FIFOURUNIFG requests an interrupt service routine |
12 | FIFOEMPTYIFG | R | 0h | Masked interrupt status for FIFOEMPTYIFG 0h = FIFOEMPTYIFG does not request an interrupt service routine 1h = FIFOEMPTYIFG requests an interrupt service routine |
11 | FIFO3B4IFG | R | 0h | Masked interrupt status for FIFO3B4IFG 0h = FIFO3B4IFG does not request an interrupt service routine 1h = FIFO3B4IFG requests an interrupt service routine |
10 | FIFO1B2IFG | R | 0h | Masked interrupt status for FIFO1B2IFG 0h = FIFO1B2IFG does not request an interrupt service routine 1h = FIFO1B2IFG requests an interrupt service routine |
9 | FIFO1B4IFG | R | 0h | Masked interrupt status for FIFO1B4IFG 0h = FIFO1B4IFG does not request an interrupt service routine 1h = FIFO1B4IFG requests an interrupt service routine |
8 | FIFOFULLIFG | R | 0h | Masked interrupt status for FIFOFULLIFG 0h = FIFOFULLIFG does not request an interrupt service routine 1h = FIFOFULLIFG requests an interrupt service routine |
7-2 | RESERVED | R | 0h | |
1 | MODRDYIFG | R | 0h | Masked interrupt status for MODRDYIFG 0h = MODRDYIFG does not request an interrupt service routine 1h = MODRDYIFG requests an interrupt service routine |
0 | RESERVED | R | 0h |
ISET is shown in Figure 14-23 and described in Table 14-24.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | W | 0h | |
14 | DMADONEIFG | W | 0h | Sets DMADONEIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to DMADONEIFG is set |
13 | FIFOURUNIFG | W | 0h | Sets FIFOURUNIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOURUNIFG is set |
12 | FIFOEMPTYIFG | W | 0h | Sets FIFOEMPTYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOEMPTYIFG is set |
11 | FIFO3B4IFG | W | 0h | Sets FIFO3B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO3B4IFG is set |
10 | FIFO1B2IFG | W | 0h | Sets FIFO1B2IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B2IFG is set |
9 | FIFO1B4IFG | W | 0h | Sets FIFO1B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B4IFG is set |
8 | FIFOFULLIFG | W | 0h | Sets FIFOFULLIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOFULLIFG is set |
7-2 | RESERVED | W | 0h | |
1 | MODRDYIFG | W | 0h | Sets MODRDYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to MODRDYIFG is set |
0 | RESERVED | W | 0h |
ICLR is shown in Figure 14-24 and described in Table 14-25.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMADONEIFG | FIFOURUNIFG | FIFOEMPTYIFG | FIFO3B4IFG | FIFO1B2IFG | FIFO1B4IFG | FIFOFULLIFG |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODRDYIFG | RESERVED | |||||
W-0h | W-0h | W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | W | 0h | |
14 | DMADONEIFG | W | 0h | Clears DMADONEIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to DMADONEIFG is cleared |
13 | FIFOURUNIFG | W | 0h | Clears FIFOURUNIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOURUNIFG is cleared |
12 | FIFOEMPTYIFG | W | 0h | Clears FIFOEMPTYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOEMPTYIFG is cleared |
11 | FIFO3B4IFG | W | 0h | Clears FIFO3B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO3B4IFG is cleared |
10 | FIFO1B2IFG | W | 0h | Clears FIFO1B2IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B2IFG is cleared |
9 | FIFO1B4IFG | W | 0h | Clears FIFO1B4IFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFO1B4IFG is cleared |
8 | FIFOFULLIFG | W | 0h | Clears FIFOFULLIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to FIFOFULLIFG is cleared |
7-2 | RESERVED | W | 0h | |
1 | MODRDYIFG | W | 0h | Clears MODRDYIFG in RIS register 0h = Writing a 0 has no effect 1h = RIS bit corresponding to MODRDYIFG is cleared |
0 | RESERVED | W | 0h |
EVT_MODE is shown in Figure 14-25 and described in Table 14-26.
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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT1_CFG | INT0_CFG | |||||
R/W-0h | R-2h | R-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-2 | EVT1_CFG | R | 2h | Event line mode select for event corresponding to none.GEN_EVENT 0h = The interrupt or event line is disabled. 1h = Event handled by software. Software must clear the associated RIS flag. 2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | INT0_CFG | R | 1h | Event line mode select for event corresponding to none.CPU_INT 0h = The interrupt or event line is disabled. 1h = Event handled by software. Software must clear the associated RIS flag. 2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. |
DESC is shown in Figure 14-26 and described in Table 14-27.
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This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-311h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | RESERVED | MAJREV | MINREV | ||||||||||||
R-0h | R- | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 311h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. |
15-12 | FEATUREVER | R | 0h | Feature Set for the module *instance* |
11-8 | RESERVED | R | 0h | |
7-4 | MAJREV | R | 0h | Major rev of the IP |
3-0 | MINREV | R | 0h | Minor rev of the IP |
CTL0 is shown in Figure 14-27 and described in Table 14-28.
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Control 0 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DFM | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RES | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R/W | 0h | |
16 | DFM | R/W | 0h | This bit defines the DAC input data format. 0h = Straight binary 1h = Twos complement |
15-9 | RESERVED | R/W | 0h | |
8 | RES | R/W | 0h | These bits define the DAC output voltage resolution. 0h = 8-bits resolution 1h = 12-bit resolution |
7-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/W | 0h | This bit enables the DAC module. 0h = DAC is disabled 1h = DAC is enabled |
CTL1 is shown in Figure 14-28 and described in Table 14-29.
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Control 1 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | OPS | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REFSN | REFSP | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AMPHIZ | AMPEN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | 0h | |
24 | OPS | R/W | 0h | These bits select the DAC output on device pin. 0h = No connect. Both DAC output switches are open. 1h = OUT0 output is selected |
23-10 | RESERVED | R/W | 0h | |
9 | REFSN | R/W | 0h | This bit selects the DAC voltage reference source + input. 0h = VEREFN pin as VR- 1h = Analog supply (VSSA) as VR- |
8 | REFSP | R/W | 0h | This bit selects the DAC voltage reference source + input. 0h = Analog supply (VDDA) as VR+ 1h = VEREFP pin as VR+ |
7-2 | RESERVED | R/W | 0h | |
1 | AMPHIZ | R/W | 0h | AMPHIZ - amplifier output value 0 : amplifier output is high impedance 1 : amplifier output is pulled down to ground 0h = HiZ when disable 1h = dacout pulldown when disable |
0 | AMPEN | R/W | 0h | AMP_EN - output amplifier enabled or disabled 0 : disabled 1 : enabled 0h = disable 1h = enable |
CTL2 is shown in Figure 14-29 and described in Table 14-30.
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Control 2 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMATRIGEN | ||||||
R/W-0h | RH/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FIFOTRIGSEL | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FIFOTH | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FIFOEN | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | 0h | |
24 | DMATRIGEN | RH/W | 0h | This bit enables the DMA trigger generation mechanism. When this bit is set along with FIFOEN, the DMA trigger is generated based on the empty FIFO locations qualified by FIFOTH settings. This bit should be
cleared by software to stop further DMA triggers. 0h = DMA trigger generation mechanism is disabled 1h = DMA trigger generation mechanism is enabled |
23-18 | RESERVED | R/W | 0h | |
17-16 | FIFOTRIGSEL | R/W | 0h | These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted, the data from FIFO (as indicated by read pointer) is moved into internal DAC data register. 0h = Sample time generator output 1h = Hardware trigger-0 from event fabric 2h = Reserved - unimplemented 3h = Reserved - unimplemented |
15-10 | RESERVED | R/W | 0h | |
9-8 | FIFOTH | R/W | 0h | These bits determine the FIFO threshold. In case of DMA based operation, DAC generates new DMA trigger when the number of empty locations in FIFO match the selected FIFO threshold level. In case of CPU based
operation, the FIFO threshold bits are don't care and FIFO level is directly indicated through the respective bits in the RIS register. 0h = One fourth of the FIFO locations are empty 1h = Half of the FIFO locations are empty 2h = Three fourth of the FIFO locations are empty 3h = Reserved value. Defaults to same effect as FIFOTH = 0 (One fourth of the FIFO locations are empty). |
7-1 | RESERVED | R/W | 0h | |
0 | FIFOEN | R/W | 0h | This bit enables the FIFO and the FIFO hardware control state machine. 0h = FIFO is disabled 1h = FIFO is enabled |
CTL3 is shown in Figure 14-30 and described in Table 14-31.
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Control 3 register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | STIMCONFIG | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STIMEN | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | 0h | |
11-8 | STIMCONFIG | R/W | 0h | These bits are used to configure the trigger rate from the sample time generator. The STIMCONFIG values 10 to 15 are reserved and default to same effect as value 0 (500SPS). 0h = Trigger rate is 500 sps (clock divide value is 4000) 1h = Trigger rate is 1 ksps (clock divide value is 2000) 2h = Trigger rate is 2 ksps (clock divide value is 1000) 3h = Trigger rate is 4 ksps (clock divide value is 500) 4h = Trigger rate is 8 ksps (clock divide value is 250) 5h = Trigger rate is 16 ksps (clock divide value is 125) 6h = Trigger rate is 100 ksps (clock divide value is 20) 7h = Trigger rate is 200 ksps (clock divide value is 10) 8h = Trigger rate is 500 ksps (clock divide value is 4) 9h = Trigger rate is 1 Msps (clock divide value is 2) |
7-1 | RESERVED | R/W | 0h | |
0 | STIMEN | R/W | 0h | This bit enables the sample time generator. 0h = Sample time generator is disabled 1h = Sample time generator is enabled |
CALCTL is shown in Figure 14-31 and described in Table 14-32.
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Calibration control register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CALSEL | CALON | |||||
R/W-0h | RH/W-0h | RH/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | CALSEL | RH/W | 0h | This bit is used to select between factory trim or self calibration trim. 0h (R/W) = Factory Trim : Factory Trim Calibration Values are used when calibration is enabled 1h (R/W) = Self Calibration Trim : Self Calibration Trim Values are used when calibration is enabled |
0 | CALON | RH/W | 0h | This bit when set initiates the DAC offset error calibration sequence and is automatically reset when the offset error calibration completes. 0h = Offset error calibration is not active 1h = Initiate offset error calibration or offset error calibration is already in progress |
CALDATA is shown in Figure 14-32 and described in Table 14-33.
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This is the offset error calibration data register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA | ||||||||||||||||||||||||||||||
R-0h | RH-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | |
6-0 | DATA | RH | 0h | DAC offset error calibration data. The DAC offset error calibration data is represented in twos complement format providing a range of –64 to +63. This is read-only bit, reflecting the calibration data. Writing to this register will have no effect, it will not change the calibration value. |
DATA0 is shown in Figure 14-33 and described in Table 14-34.
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Data 0 register. This register can be written with one 8-bit or one 12-bit digital input data.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA_VALUE | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | 0h | |
11-0 | DATA_VALUE | R/W | 0h | This is the data written for digital to analog conversion. |