SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 3-9 lists the memory-mapped registers for the CPUSS registers. All register offset addresses not listed in Table 3-9 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
10E0h | EVT_MODE | Event Mode | Go | |
10FCh | DESC | Module Description | Go | |
1100h | IIDX | Interrupt index | CPU_INT_GROUP0 | Go |
1108h | IMASK | Interrupt mask | CPU_INT_GROUP0 | Go |
1110h | RIS | Raw interrupt status | CPU_INT_GROUP0 | Go |
1118h | MIS | Masked interrupt status | CPU_INT_GROUP0 | Go |
1120h | ISET | Interrupt set | CPU_INT_GROUP0 | Go |
1128h | ICLR | Interrupt clear | CPU_INT_GROUP0 | Go |
1130h | IIDX | Interrupt index | CPU_INT_GROUP1 | Go |
1138h | IMASK | Interrupt mask | CPU_INT_GROUP1 | Go |
1140h | RIS | Raw interrupt status | CPU_INT_GROUP1 | Go |
1148h | MIS | Masked interrupt status | CPU_INT_GROUP1 | Go |
1150h | ISET | Interrupt set | CPU_INT_GROUP1 | Go |
1158h | ICLR | Interrupt clear | CPU_INT_GROUP1 | Go |
1160h | IIDX | Interrupt index | CPU_INT_GROUP2 | Go |
1168h | IMASK | Interrupt mask | CPU_INT_GROUP2 | Go |
1170h | RIS | Raw interrupt status | CPU_INT_GROUP2 | Go |
1178h | MIS | Masked interrupt status | CPU_INT_GROUP2 | Go |
1180h | ISET | Interrupt set | CPU_INT_GROUP2 | Go |
1188h | ICLR | Interrupt clear | CPU_INT_GROUP2 | Go |
1190h | IIDX | Interrupt index | CPU_INT_GROUP3 | Go |
1198h | IMASK | Interrupt mask | CPU_INT_GROUP3 | Go |
11A0h | RIS | Raw interrupt status | CPU_INT_GROUP3 | Go |
11A8h | MIS | Masked interrupt status | CPU_INT_GROUP3 | Go |
11B0h | ISET | Interrupt set | CPU_INT_GROUP3 | Go |
11B8h | ICLR | Interrupt clear | CPU_INT_GROUP3 | Go |
11C0h | IIDX | Interrupt index | CPU_INT_GROUP4 | Go |
11C8h | IMASK | Interrupt mask | CPU_INT_GROUP4 | Go |
11D0h | RIS | Raw interrupt status | CPU_INT_GROUP4 | Go |
11D8h | MIS | Masked interrupt status | CPU_INT_GROUP4 | Go |
11E0h | ISET | Interrupt set | CPU_INT_GROUP4 | Go |
11E8h | ICLR | Interrupt clear | CPU_INT_GROUP4 | Go |
1300h | CTL | Prefetch/Cache control | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-10 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
EVT_MODE is shown in Figure 3-5 and described in Table 3-11.
Return to the Summary Table.
Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_CFG | ||||||
R- | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1-0 | INT_CFG | R | 1h | Event line mode select
0h = The interrupt or event line is disabled. 1h = Event handled by software. Software must clear the associated RIS flag. 2h = Event handled by hardware. The hardware (another module) clears automatically the associated RIS flag. |
DESC is shown in Figure 3-6 and described in Table 3-12.
Return to the Summary Table.
This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-2711h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | RESERVED | MAJREV | MINREV | ||||||||||||
R-0h | R- | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 2711h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. |
15-12 | FEATUREVER | R | 0h | Feature Set for the module *instance* |
11-8 | RESERVED | R | 0h | |
7-4 | MAJREV | R | 0h | Major rev of the IP |
3-0 | MINREV | R | 0h | Minor rev of the IP |
IIDX is shown in Figure 3-7 and described in Table 3-13.
Return to the Summary Table.
Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 1h = Interrupt 0 2h = Interrupt 1 3h = Interrupt 2 4h = Interrupt 3 5h = Interrupt 4 6h = Interrupt 5 7h = Interrupt 6 8h = Interrupt 7 |
IMASK is shown in Figure 3-8 and described in Table 3-14.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-FFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | FFh | Masks the corresponding interrupt
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
RIS is shown in Figure 3-9 and described in Table 3-15.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Raw interrupt status for INT
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
MIS is shown in Figure 3-10 and described in Table 3-16.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Masked interrupt status for INT0
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ISET is shown in Figure 3-11 and described in Table 3-17.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Sets INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ICLR is shown in Figure 3-12 and described in Table 3-18.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Clears INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
IIDX is shown in Figure 3-13 and described in Table 3-19.
Return to the Summary Table.
Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 1h = Interrupt 0 2h = Interrupt 1 3h = Interrupt 2 4h = Interrupt 3 5h = Interrupt 4 6h = Interrupt 5 7h = Interrupt 6 8h = Interrupt 7 |
IMASK is shown in Figure 3-14 and described in Table 3-20.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-FFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | FFh | Masks the corresponding interrupt
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
RIS is shown in Figure 3-15 and described in Table 3-21.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Raw interrupt status for INT
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
MIS is shown in Figure 3-16 and described in Table 3-22.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Masked interrupt status for INT0
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ISET is shown in Figure 3-17 and described in Table 3-23.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Sets INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ICLR is shown in Figure 3-18 and described in Table 3-24.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Clears INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
IIDX is shown in Figure 3-19 and described in Table 3-25.
Return to the Summary Table.
Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 1h = Interrupt 0 2h = Interrupt 1 3h = Interrupt 2 4h = Interrupt 3 5h = Interrupt 4 6h = Interrupt 5 7h = Interrupt 6 8h = Interrupt 7 |
IMASK is shown in Figure 3-20 and described in Table 3-26.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-FFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | FFh | Masks the corresponding interrupt
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
RIS is shown in Figure 3-21 and described in Table 3-27.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Raw interrupt status for INT
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
MIS is shown in Figure 3-22 and described in Table 3-28.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Masked interrupt status for INT0
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ISET is shown in Figure 3-23 and described in Table 3-29.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Sets INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ICLR is shown in Figure 3-24 and described in Table 3-30.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Clears INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
IIDX is shown in Figure 3-25 and described in Table 3-31.
Return to the Summary Table.
Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 1h = Interrupt 0 2h = Interrupt 1 3h = Interrupt 2 4h = Interrupt 3 5h = Interrupt 4 6h = Interrupt 5 7h = Interrupt 6 8h = Interrupt 7 |
IMASK is shown in Figure 3-26 and described in Table 3-32.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-FFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | FFh | Masks the corresponding interrupt
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
RIS is shown in Figure 3-27 and described in Table 3-33.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Raw interrupt status for INT
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
MIS is shown in Figure 3-28 and described in Table 3-34.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Masked interrupt status for INT0
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ISET is shown in Figure 3-29 and described in Table 3-35.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Sets INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ICLR is shown in Figure 3-30 and described in Table 3-36.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Clears INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
IIDX is shown in Figure 3-31 and described in Table 3-37.
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Interrupt index register. This read-only register provides the interrupt index of the pending interrupt with the highest priority. It also indicates if no interrupt is pending. The priority order is fixed: lower index equals higher priority. Alternatively to the use of IIDX, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt or indicate that no interrupt is pending. Only interrupts which are selected via IMASK are indicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
0h = No pending interrupt 1h = Interrupt 0 2h = Interrupt 1 3h = Interrupt 2 4h = Interrupt 3 5h = Interrupt 4 6h = Interrupt 5 7h = Interrupt 6 8h = Interrupt 7 |
IMASK is shown in Figure 3-32 and described in Table 3-38.
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Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-FFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | FFh | Masks the corresponding interrupt
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
RIS is shown in Figure 3-33 and described in Table 3-39.
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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Raw interrupt status for INT
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
MIS is shown in Figure 3-34 and described in Table 3-40.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | INT | R | 0h | Masked interrupt status for INT0
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ISET is shown in Figure 3-35 and described in Table 3-41.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Sets INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
ICLR is shown in Figure 3-36 and described in Table 3-42.
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Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||||||||||||||||||
W-0h | W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | W | 0h | |
7-0 | INT | W | 0h | Clears INT in RIS register
1h = Interrupt 0 2h = Interrupt 1 4h = Interrupt 2 8h = Interrupt 3 10h = Interrupt 4 20h = Interrupt 5 40h = Interrupt 6 80h = Interrupt 7 |
CTL is shown in Figure 3-37 and described in Table 3-43.
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Flash prefetch and cache control register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LITEN | ICACHE | PREFETCH | ||||
R/W-0h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | |
2 | LITEN | R/W | 1h | Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals 0h = Literal caching disabled 1h = Literal caching enabled |
1 | ICACHE | R/W | 1h | Used to enable/disable Instruction caching on flash access.
0h = Disable instruction caching. 1h = Enable instruction caching. |
0 | PREFETCH | R/W | 1h | Used to enable/disable instruction prefetch to Flash.
0h = Disable instruction prefetch. 1h = Enable instruction prefetch. |