SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 12-7 lists the memory-mapped registers for the OA registers. All register offset addresses not listed in Table 12-7 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
814h | STAT | Status Register | Go | |
1010h | CLKOVR | Clock Override | Go | |
101Ch | PWRCTL | Power Control | Go | |
1100h | CTL | Control Register | Go | |
1108h | CFG | Configuration Register | Go | |
1118h | STAT | Status Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 12-8 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
PWREN is shown in Figure 12-11 and described in Table 12-9.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 12-12 and described in Table 12-10.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 12-13 and described in Table 12-11.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CLKOVR is shown in Figure 12-14 and described in Table 12-12.
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This register overrides the functional clock request by this peripheral to the system
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RUN_STOP | OVERRIDE | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | RUN_STOP | R/W | 0h | If OVERRIDE is enabled, this register is used to manually control the peripheral's clock request to the system
0h = Run/ungate functional clock 1h = Stop/gate functional clock |
0 | OVERRIDE | R/W | 0h | Unlocks the functionality of RUN_STOP to override the automatic peripheral clock request
0h = Override disabled 1h = Override enabled |
PWRCTL is shown in Figure 12-15 and described in Table 12-13.
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This register controls if a peripheral is disabled if it is in idle state.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AUTO_OFF | ||||||
R/W- | R/W-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | |
0 | AUTO_OFF | R/W | 1h | When set the peripheral will remove its local IP “request for enable” so that it can be disabled if no other entities in the system are requesting it to be enabled.
0h = Disable automatic power off function 1h = Enable automatic power off function |
CTL is shown in Figure 12-16 and described in Table 12-14.
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Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | |
0 | ENABLE | R/W | 0h | OAxn Enable.
0h (R/W) = OAxn OFF 1h (R/W) = OAxn ON |
CFG is shown in Figure 12-17 and described in Table 12-15.
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Configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GAIN | MSEL | NSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NSEL | PSEL | OUTPIN | CHOP | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-13 | GAIN | R/W | 0h | Gain setting. Refer to TRM for enumeration information.
0h = Minmum gain value 7h = Maximum gain value. |
12-10 | MSEL | R/W | 0h | MSEL Mux selection. Please refer to the device specific data sheet for exact channels available. 0h (R/W) = no connect 1h (R/W) = external pin OAn-1 2h (R/W) = VSS 3h (R/W) = DAC12 Output 4h (R/W) = OA[n-1]Rtop |
9-7 | NSEL | R/W | 0h | Negative OA input selection. Please refer to the device specific data sheet for exact channels available. 0h (R/W) = no connect 1h (R/W) = external pin OAn-0 2h (R/W) = external pin OAn-1 3h (R/W) = OA[n+1]Rbot 4h (R/W) = OA[n]Rtap 5h (R/W) = OA[n]Rtop 6h (R/W) = Spare input |
6-3 | PSEL | R/W | 0h | Positive OA input selection. Please refer to the device specific data sheet for exact channels available. 0h (R/W) = No connect 1h (R/W) = external pin OA+0 2h (R/W) = external pin OAn+1 3h (R/W) = DAC12OUT 4h (R/W) = DAC8OUT 5h (R/W) = VREF Channel 6h (R/W) = OA[n-1]Rtop 7h (R/W) = GPAMP_OUT_INT Input 8h = Internal Grouund Connection |
2 | OUTPIN | R/W | 0h | Enable output pin
0h (R/W) = Output pin disabled 1h (R/W) = Output pin enabled |
1-0 | CHOP | R/W | 0h | Chopping enable.
0h (R/W) = Chopping disable. 1h (R/W) = Standard chopping enable. 2h (R/W) = Chop with post average on. Requires output to be connect to ADC in average mode. |
STAT is shown in Figure 12-18 and described in Table 12-16.
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Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDY | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | |
0 | RDY | R | 0h | OA ready status.
0h (R) = OAxn is not ready. 1h (R) = OAxn is ready. |