SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 1-36 lists the memory-mapped registers for the FACTORYREGION registers. All register offset addresses not listed in Table 1-36 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
41C40000h | TRACEID | Trace identifier | Go | |
41C40004h | DEVICEID | Device identifier | Go | |
41C40008h | USERID | Device variant identifier | Go | |
41C4000Ch | BSLPIN_UART | Go | ||
41C40010h | BSLPIN_I2C | Go | ||
41C40014h | BSLPIN_INVOKE | Go | ||
41C40018h | SRAMFLASH | Go | ||
41C4001Ch | PLLSTARTUP0_4_8MHZ | Go | ||
41C40020h | PLLSTARTUP1_4_8MHZ | System PLL Parameter 1 MMR --- Data from Flash Table Lookup | Go | |
41C40024h | PLLSTARTUP0_8_16MHZ | Go | ||
41C40028h | PLLSTARTUP1_8_16MHZ | System PLL Parameter 1 MMR --- Data from Flash Table Lookup | Go | |
41C4002Ch | PLLSTARTUP0_16_32MHZ | Go | ||
41C40030h | PLLSTARTUP1_16_32MHZ | System PLL Parameter 1 MMR --- Data from Flash Table Lookup | Go | |
41C40034h | PLLSTARTUP0_32_48MHZ | Go | ||
41C40038h | PLLSTARTUP1_32_48MHZ | System PLL Parameter 1 MMR --- Data from Flash Table Lookup | Go | |
41C4003Ch | TEMP_SENSE0 | Temperature sensor room temperature calibration code. This is ADC conversion results of temperature sensor output voltage. Included in BOOTCRC calculation. | Go | |
41C40040h | RESERVED0 | Go | ||
41C40044h | RESERVED1 | Go | ||
41C40048h | RESERVED2 | Go | ||
41C4004Ch | RESERVED3 | Go | ||
41C40050h | RESERVED4 | Go | ||
41C40054h | RESERVED5 | Go | ||
41C40058h | RESERVED6 | Go | ||
41C4005Ch | RESERVED7 | Go | ||
41C40060h | RESERVED8 | Go | ||
41C40064h | RESERVED9 | Go | ||
41C40068h | RESERVED10 | Go | ||
41C4006Ch | RESERVED11 | Go | ||
41C40070h | RESERVED12 | Go | ||
41C40074h | RESERVED13 | Go | ||
41C40078h | RESERVED14 | Go | ||
41C4007Ch | BOOTCRC | BOOTCRC records the 32-bit CRC of all locations in OPEN including reserved locations. | Go |
Complex bit access types are encoded to fit into small table cells. Table 1-37 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
TRACEID is shown in Figure 1-29 and described in Table 1-38.
Return to the Summary Table.
Unique value per device shipped
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R- | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R | 0h |
DEVICEID is shown in Figure 1-30 and described in Table 1-39.
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Device identifier (die revision specific)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
VERSION | PARTNUM | ||||||
R-0h | R-BB88h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PARTNUM | |||||||
R-BB88h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARTNUM | MANUFACTURER | ||||||
R-BB88h | R-17h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MANUFACTURER | ALWAYS_1 | ||||||
R-17h | R-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | VERSION | R | 0h | Revision of the device |
27-12 | PARTNUM | R | BB88h | Part number of the device |
11-1 | MANUFACTURER | R | 17h | TI's JEDEC bank and company code |
0 | ALWAYS_1 | R | 1h | This is always 1 |
USERID is shown in Figure 1-31 and described in Table 1-40.
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per Connectivity format, defines the variant feature set
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
START | MAJORREV | MINORREV | |||||
R-1h | R- | R- | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VARIANT | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PART | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PART | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | START | R | 1h | |
30-28 | MAJORREV | R | 0h | Monotonic increasing value indicating a new revision of the SKU significant enough that users of the device may have to revise PCB or software design |
27-24 | MINORREV | R | 0h | Monotonic increasing value indicating a new revision of the SKU that preserves compatibility with lesser minor rev values. New capability may be introduced such that lesser minor rev numbers may not be compatible with greater if the new capability is used. |
23-16 | VARIANT | R | 0h | Bit pattern uniquely identifying the variant of a part |
15-0 | PART | R | 0h | Bit pattern that uniquely identifying a part |
BSLPIN_UART is shown in Figure 1-32 and described in Table 1-41.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UART_TXT_PF | UART_TXD_PAD | ||||||||||||||
R-2h | R-18h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UART_RXD_PF | UART_RXD_PAD | ||||||||||||||
R-2h | R-19h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | UART_TXT_PF | R | 2h | |
23-16 | UART_TXD_PAD | R | 18h | |
15-8 | UART_RXD_PF | R | 2h | |
7-0 | UART_RXD_PAD | R | 19h |
BSLPIN_I2C is shown in Figure 1-33 and described in Table 1-42.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
I2C_SCL_PF | I2C_SCL_PAD | ||||||||||||||
R-3h | R-2h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2C_SDA_PF | I2C_SDA_PAD | ||||||||||||||
R-3h | R-1h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | I2C_SCL_PF | R | 3h | |
23-16 | I2C_SCL_PAD | R | 2h | |
15-8 | I2C_SDA_PF | R | 3h | |
7-0 | I2C_SDA_PAD | R | 1h |
BSLPIN_INVOKE is shown in Figure 1-34 and described in Table 1-43.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO_REG_SEL | GPIO_PIN_SEL | ||||||
R- | R-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO_LEVEL | BSL_PAD | ||||||
R-1h | R-2Bh | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15-14 | GPIO_REG_SEL | R | 0h | |
13-8 | GPIO_PIN_SEL | R | 1h | |
7 | GPIO_LEVEL | R | 1h | |
6-0 | BSL_PAD | R | 2Bh |
SRAMFLASH is shown in Figure 1-35 and described in Table 1-44.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DATAFLASH_SZ | SRAM_SZ | ||||||
R-0h | R-20h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SRAM_SZ | |||||||
R-20h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAINNUMBANKS | MAINFLASH_SZ | |||||
R- | R-0h | R-80h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAINFLASH_SZ | |||||||
R-80h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | DATAFLASH_SZ | R | 0h | The encoding of the field is that the value of the field is an integer to be interpreted as number of KB. For example, if the value of the field id 4, then it is 4KB, if the value is 32, then 32KB, and so on. |
25-16 | SRAM_SZ | R | 20h | The encoding of the field is that the value of the field is an integer to be interpreted as number of KB. For example, if the value of the field id 4, then it is 4KB, if the value is 32, then 32KB, and so on. |
15-14 | RESERVED | R | 0h | |
13-12 | MAINNUMBANKS | R | 0h | |
11-0 | MAINFLASH_SZ | R | 80h | The encoding of the field is that the value of the field is an integer to be interpreted as number of KB. For example, if the value of the field id 4, then it is 4KB, if the value is 32, then 32KB, and so on. |
PLLSTARTUP0_4_8MHZ is shown in Figure 1-36 and described in Table 1-45.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CAPBOVERRIDE | CAPBVAL | CPCURRENT | |||||
R/W- | R/W- | R/W-4h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPCURRENT | STARTTIMELP | ||||||
R/W-4h | R/W-12h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTTIMELP | STARTTIME | ||||||
R/W-12h | R/W-16h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | |
23 | CAPBOVERRIDE | R/W | 0h | Override Enable For Cap B
0h = 0 1h = 1 |
22-18 | CAPBVAL | R/W | 0h | Override Value for Cap B |
17-12 | CPCURRENT | R/W | 4h | Charge Pump Current |
11-6 | STARTTIMELP | R/W | 12h | Startup time from Low Power Exit to Locked Clock in resolution of 1usec |
5-0 | STARTTIME | R/W | 16h | Startup time from Enable to Locked Clock in resolution of 1usec |
PLLSTARTUP1_4_8MHZ is shown in Figure 1-37 and described in Table 1-46.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LPFRESC | ||||||||||||||
R- | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPFRESC | LPFRESA | LPFCAPA | |||||||||||||
R/W-1h | R/W-2h | R/W-1Ch | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | |
22-15 | LPFRESC | R/W | 1h | Loop Filter Res C |
14-5 | LPFRESA | R/W | 2h | Loop Filter Res A |
4-0 | LPFCAPA | R/W | 1Ch | Loop Filter Cap A |
PLLSTARTUP0_8_16MHZ is shown in Figure 1-38 and described in Table 1-47.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CAPBOVERRIDE | CAPBVAL | CPCURRENT | |||||
R/W- | R/W- | R/W-5h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPCURRENT | STARTTIMELP | ||||||
R/W-5h | R/W-Bh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTTIMELP | STARTTIME | ||||||
R/W-Bh | R/W-Fh | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | |
23 | CAPBOVERRIDE | R/W | 0h | Override Enable For Cap B
0h = 0 1h = 1 |
22-18 | CAPBVAL | R/W | 0h | Override Value for Cap B |
17-12 | CPCURRENT | R/W | 5h | Charge Pump Current |
11-6 | STARTTIMELP | R/W | Bh | Startup time from Low Power Exit to Locked Clock in resolution of 1usec |
5-0 | STARTTIME | R/W | Fh | Startup time from Enable to Locked Clock in resolution of 1usec |
PLLSTARTUP1_8_16MHZ is shown in Figure 1-39 and described in Table 1-48.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LPFRESC | ||||||||||||||
R- | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPFRESC | LPFRESA | LPFCAPA | |||||||||||||
R/W-1h | R/W-1h | R/W-10h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | |
22-15 | LPFRESC | R/W | 1h | Loop Filter Res C |
14-5 | LPFRESA | R/W | 1h | Loop Filter Res A |
4-0 | LPFCAPA | R/W | 10h | Loop Filter Cap A |
PLLSTARTUP0_16_32MHZ is shown in Figure 1-40 and described in Table 1-49.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CAPBOVERRIDE | CAPBVAL | CPCURRENT | |||||
R/W- | R/W- | R/W-5h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPCURRENT | STARTTIMELP | ||||||
R/W-5h | R/W-8h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTTIMELP | STARTTIME | ||||||
R/W-8h | R/W-Ch | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | |
23 | CAPBOVERRIDE | R/W | 0h | Override Enable For Cap B
0h = 0 1h = 1 |
22-18 | CAPBVAL | R/W | 0h | Override Value for Cap B |
17-12 | CPCURRENT | R/W | 5h | Charge Pump Current |
11-6 | STARTTIMELP | R/W | 8h | Startup time from Low Power Exit to Locked Clock in resolution of 1usec |
5-0 | STARTTIME | R/W | Ch | Startup time from Enable to Locked Clock in resolution of 1usec |
PLLSTARTUP1_16_32MHZ is shown in Figure 1-41 and described in Table 1-50.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LPFRESC | ||||||||||||||
R- | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPFRESC | LPFRESA | LPFCAPA | |||||||||||||
R/W-1h | R/W-1h | R/W-10h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | |
22-15 | LPFRESC | R/W | 1h | Loop Filter Res C |
14-5 | LPFRESA | R/W | 1h | Loop Filter Res A |
4-0 | LPFCAPA | R/W | 10h | Loop Filter Cap A |
PLLSTARTUP0_32_48MHZ is shown in Figure 1-42 and described in Table 1-51.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CAPBOVERRIDE | CAPBVAL | CPCURRENT | |||||
R/W- | R/W- | R/W-5h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPCURRENT | STARTTIMELP | ||||||
R/W-5h | R/W-6h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTTIMELP | STARTTIME | ||||||
R/W-6h | R/W-Ah | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | |
23 | CAPBOVERRIDE | R/W | 0h | Override Enable For Cap B
0h = 0 1h = 1 |
22-18 | CAPBVAL | R/W | 0h | Override Value for Cap B |
17-12 | CPCURRENT | R/W | 5h | Charge Pump Current |
11-6 | STARTTIMELP | R/W | 6h | Startup time from Low Power Exit to Locked Clock in resolution of 1usec |
5-0 | STARTTIME | R/W | Ah | Startup time from Enable to Locked Clock in resolution of 1usec |
PLLSTARTUP1_32_48MHZ is shown in Figure 1-43 and described in Table 1-52.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LPFRESC | ||||||||||||||
R- | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPFRESC | LPFRESA | LPFCAPA | |||||||||||||
R/W-1h | R/W-1h | R/W-10h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | |
22-15 | LPFRESC | R/W | 1h | Loop Filter Res C |
14-5 | LPFRESA | R/W | 1h | Loop Filter Res A |
4-0 | LPFCAPA | R/W | 10h | Loop Filter Cap A |
TEMP_SENSE0 is shown in Figure 1-44 and described in Table 1-53.
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Temperature sensor room temperature calibration code. This is ADC conversion results of temperature sensor output voltage. Included in BOOTCRC calculation.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R- | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R | 0h |
RESERVED0 is shown in Figure 1-45 and described in Table 1-54.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED1 is shown in Figure 1-46 and described in Table 1-55.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED2 is shown in Figure 1-47 and described in Table 1-56.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED3 is shown in Figure 1-48 and described in Table 1-57.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED4 is shown in Figure 1-49 and described in Table 1-58.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED5 is shown in Figure 1-50 and described in Table 1-59.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED6 is shown in Figure 1-51 and described in Table 1-60.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED7 is shown in Figure 1-52 and described in Table 1-61.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED8 is shown in Figure 1-53 and described in Table 1-62.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED9 is shown in Figure 1-54 and described in Table 1-63.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED10 is shown in Figure 1-55 and described in Table 1-64.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED11 is shown in Figure 1-56 and described in Table 1-65.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED12 is shown in Figure 1-57 and described in Table 1-66.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED13 is shown in Figure 1-58 and described in Table 1-67.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RESERVED14 is shown in Figure 1-59 and described in Table 1-68.
Return to the Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
BOOTCRC is shown in Figure 1-60 and described in Table 1-69.
Return to the Summary Table.
BOOTCRC records the 32-bit CRC of all locations in OPEN including reserved locations.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R- | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R | 0h |