SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 25-26 lists the memory-mapped registers for the Timers (TIMx) registers. All register offset addresses not listed in Table 25-26 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
400h | FSUB_0 | Subsciber Port 0 | Go | |
404h | FSUB_1 | Subscriber Port 1 | Go | |
444h | FPUB_0 | Publisher Port 0 | Go | |
448h | FPUB_1 | Publisher Port 1 | Go | |
800h | PWREN | Power enable | Go | |
804h | RSTCTL | Reset Control | Go | |
814h | STAT | Status Register | Go | |
1000h | CLKDIV | Clock Divider | Go | |
1008h | CLKSEL | Clock Select for Ultra Low Power peripherals | Go | |
1018h | PDBGCTL | Peripheral Debug Control | Go | |
1020h | IIDX | Interrupt index | CPU_INT | Go |
1028h | IMASK | Interrupt mask | CPU_INT | Go |
1030h | RIS | Raw interrupt status | CPU_INT | Go |
1038h | MIS | Masked interrupt status | CPU_INT | Go |
1040h | ISET | Interrupt set | CPU_INT | Go |
1048h | ICLR | Interrupt clear | CPU_INT | Go |
1050h | IIDX | Interrupt index | GEN_EVENT0 | Go |
1058h | IMASK | Interrupt mask | GEN_EVENT0 | Go |
1060h | RIS | Raw interrupt status | GEN_EVENT0 | Go |
1068h | MIS | Masked interrupt status | GEN_EVENT0 | Go |
1070h | ISET | Interrupt set | GEN_EVENT0 | Go |
1078h | ICLR | Interrupt clear | GEN_EVENT0 | Go |
1080h | IIDX | Interrupt index | GEN_EVENT1 | Go |
1088h | IMASK | Interrupt mask | GEN_EVENT1 | Go |
1090h | RIS | Raw interrupt status | GEN_EVENT1 | Go |
1098h | MIS | Masked interrupt status | GEN_EVENT1 | Go |
10A0h | ISET | Interrupt set | GEN_EVENT1 | Go |
10A8h | ICLR | Interrupt clear | GEN_EVENT1 | Go |
10E0h | EVT_MODE | Event Mode | Go | |
10FCh | DESC | Module Description | Go | |
1100h | CCPD | CCP Direction | Go | |
1104h | ODIS | Output Disable | Go | |
1108h | CCLKCTL | Counter Clock Control Register | Go | |
110Ch | CPS | Clock Prescale Register | Go | |
1110h | CPSV | Clock prescale count status register | Go | |
1114h | CTTRIGCTL | Timer Cross Trigger Control Register | Go | |
111Ch | CTTRIG | Timer Cross Trigger Register | Go | |
1120h | FSCTL | Fault Source Control | Go | |
1124h | GCTL | Global control register | Go | |
1800h | CTR | Counter Register | Go | |
1804h | CTRCTL | Counter Control Register | Go | |
1808h | LOAD | Load Register | Go | |
1810h + formula | CC_01[y] | Capture or Compare Register 0/1 | Go | |
1818h + formula | CC_23[y] | Capture or Compare Register 0/1 | Go | |
1820h + formula | CC_45[y] | The CC_45 register are a registers which can be used as compare to the current CTR to create an events CC4U, CC4D, CC5U and CC5D. | Go | |
1830h + formula | CCCTL_01[y] | Capture or Compare Control Registers | Go | |
1838h + formula | CCCTL_23[y] | Capture or Compare Control Registers 0/1 | Go | |
1840h + formula | CCCTL_45[y] | Capture or Compare Control Registers 2/3 | Go | |
1850h + formula | OCTL_01[y] | CCP Output Control Registers 4/5 | Go | |
1858h + formula | OCTL_23[y] | CCP Output Control Registers 0/1 | Go | |
1870h + formula | CCACT_01[y] | Capture or Compare Action Registers 2/3 | Go | |
1878h + formula | CCACT_23[y] | Capture or Compare Action Registers 0/1 | Go | |
1880h + formula | IFCTL_01[y] | Input Filter Control Register 0/1 | Go | |
1888h + formula | IFCTL_23[y] | Input Filter Control Register 2/3 | Go | |
18A0h | PL | Phase Load Register | Go | |
18A4h | DBCTL | Dead Band insertion control register | Go | |
18B0h | TSEL | Trigger Select Register | Go | |
18B4h | RC | Repeat counter Register | Go | |
18B8h | RCLD | Repeat counter load Register | Go | |
18BCh | QDIR | QEI Count Direction Register | Go | |
18D0h | FCTL | Fault Control Register | Go | |
18D4h | FIFCTL | Fault input Filter control register | Go |
Complex bit access types are encoded to fit into small table cells. Table 25-27 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
K | K | Write protected by a key |
W | W | Write |
WK | W K | Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
FSUB_0 is shown in Figure 25-41 and described in Table 25-28.
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Subscriber port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
FSUB_1 is shown in Figure 25-42 and described in Table 25-29.
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Subscriber port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
FPUB_0 is shown in Figure 25-43 and described in Table 25-30.
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Publisher port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
FPUB_1 is shown in Figure 25-44 and described in Table 25-31.
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Publisher port
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHANID | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3-0 | CHANID | R/W | 0h | 0 = disconnected. 1-15 = connected to channelID = CHANID. 0h = A value of 0 specifies that the event is not connected Fh = Consult your device data sheet as the actual allowed maximum may be less than 15. |
PWREN is shown in Figure 25-45 and described in Table 25-32.
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Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R/W-0h | K-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change
26h = KEY to allow write access to this register |
23-1 | RESERVED | R/W | 0h | |
0 | ENABLE | K | 0h | Enable the power KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 25-46 and described in Table 25-33.
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Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
W-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key
B1h = KEY to allow write access to this register |
23-2 | RESERVED | W | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
STAT is shown in Figure 25-47 and described in Table 25-34.
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peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R- | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R- | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0h | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CLKDIV is shown in Figure 25-48 and described in Table 25-35.
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This register is used to specify module-specific divide ratio of the functional clock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock
0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8 |
CLKSEL is shown in Figure 25-49 and described in Table 25-36.
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Clock Source Select Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSCLK_SEL | MFCLK_SEL | LFCLK_SEL | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | BUSCLK_SEL | R/W | 0h | Selects BUSCLK as clock source if enabled
0h = Does not select this clock as a source 1h = Select this clock as a source |
2 | MFCLK_SEL | R/W | 0h | Selects MFCLK as clock source if enabled
0h = Does not select this clock as a source 1h = Select this clock as a source |
1 | LFCLK_SEL | R/W | 0h | Selects LFCLK as clock source if enabled
0h = Does not select this clock as a source 1h = Select this clock as a source |
0 | RESERVED | R/W | 0h |
PDBGCTL is shown in Figure 25-50 and described in Table 25-37.
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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W- | R/W-1h | R/W-1h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1 | SOFT | R/W | 1h | Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption |
0 | FREE | R/W | 1h | Free run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 1h = The peripheral ignores the state of the Core Halted input |
IIDX is shown in Figure 25-51 and described in Table 25-38.
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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
00h = No interrupt pending 01h = Interrupt Source: Zero event (Z) 02h = nterrupt Source: Load event (L) 05h = Interrupt Source: Capture or compare down event (CCD0) 06h = Interrupt Source: Capture or compare down event (CCD1) 07h = Interrupt Source: Capture or compare down event (CCD2) 08h = Interrupt Source: Capture or compare down event (CCD3) 09h = Interrupt Source: Capture or compare up event (CCU0) 0Ah = Interrupt Source: Capture or compare up event (CCU1) 0Bh = Interrupt Source: Capture or compare up event (CCU2) 0Ch = Interrupt Source: Capture or compare up event (CCU3) 0Dh = Interrupt Source: Compare down event (CCD4) 0Eh = Interrupt Source: Compare down event (CCD5) 0Fh = Interrupt Source: Compare down event (CCU4) 10h = Interrupt Source: Compare down event (CCU5) 19h = Interrupt Source: Fault Event generated an interrupt. (F) 1Ah = Interrupt Source: Trigger overflow (TOV) 1Bh = Interrupt Source: Repeat Counter Zero (REPC) 1Ch = Interrupt Source: Direction Change (DC) 1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR) |
IMASK is shown in Figure 25-52 and described in Table 25-39.
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Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W- | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | 0h | |
28 | QEIERR | R/W | 0h | QEIERR Event mask
0h = Disable Event 1h = Enable Event |
27 | DC | R/W | 0h | Direction Change Event mask
0h = Disable Event 1h = Enable Event |
26 | REPC | R/W | 0h | Repeat Counter Zero Event mask
0h = Disable Event 1h = Enable Event |
25 | TOV | R/W | 0h | Trigger Overflow Event mask
0h = Disable Event 1h = Enable Event |
24 | F | R/W | 0h | Fault Event mask
0h = Disable Event 1h = Enable Event |
23-16 | RESERVED | R/W | 0h | |
15 | CCU5 | R/W | 0h | Compare UP event mask CCP5
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
14 | CCU4 | R/W | 0h | Compare UP event mask CCP4
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
13 | CCD5 | R/W | 0h | Compare DN event mask CCP5
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
12 | CCD4 | R/W | 0h | Compare DN event mask CCP4
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
11 | CCU3 | R/W | 0h | Capture or Compare UP event mask CCP3
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
10 | CCU2 | R/W | 0h | Capture or Compare UP event mask CCP2
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9 | CCU1 | R/W | 0h | Capture or Compare UP event mask CCP1
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
8 | CCU0 | R/W | 0h | Capture or Compare UP event mask CCP0
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | CCD3 | R/W | 0h | Capture or Compare DN event mask CCP3
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | CCD2 | R/W | 0h | Capture or Compare DN event mask CCP2
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
5 | CCD1 | R/W | 0h | Capture or Compare DN event mask CCP1
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | CCD0 | R/W | 0h | Capture or Compare DN event mask CCP0
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3-2 | RESERVED | R/W | 0h | |
1 | L | R/W | 0h | Load Event mask
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | Z | R/W | 0h | Zero Event mask
0h = Disable Event 1h = Enable Event |
RIS is shown in Figure 25-53 and described in Table 25-40.
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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | |
28 | QEIERR | R | 0h | QEIERR, set on an incorrect state transition on the encoder interface.
0h = Event Cleared 1h = Event Set |
27 | DC | R | 0h | Direction Change
0h = Event Cleared 1h = Event Set |
26 | REPC | R | 0h | Repeat Counter Zero
0h = Event Cleared 1h = Event Set |
25 | TOV | R | 0h | Trigger overflow
0h = Event Cleared 1h = Event Set |
24 | F | R | 0h | Fault
0h = Event Cleared 1h = Event Set |
23-16 | RESERVED | R | 0h | |
15 | CCU5 | R | 0h | Compare up event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
14 | CCU4 | R | 0h | Compare up event generated an interrupt CCU4
0h = Event Cleared 1h = Event Set |
13 | CCD5 | R | 0h | Compare down event generated an interrupt CCD5
0h = Event Cleared 1h = Event Set |
12 | CCD4 | R | 0h | Compare down event generated an interrupt CCD4
0h = Event Cleared 1h = Event Set |
11 | CCU3 | R | 0h | Capture or compare up event generated an interrupt CCP3 0h = Event Cleared 1h = Event Set |
10 | CCU2 | R | 0h | Capture or compare up event generated an interrupt CCP2 0h = Event Cleared 1h = Event Set |
9 | CCU1 | R | 0h | Capture or compare up event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
8 | CCU0 | R | 0h | Capture or compare up event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
7 | CCD3 | R | 0h | Capture or compare down event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
6 | CCD2 | R | 0h | Capture or compare down event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
5 | CCD1 | R | 0h | Capture or compare down event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
4 | CCD0 | R | 0h | Capture or compare down event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
3-2 | RESERVED | R | 0h | |
1 | L | R | 0h | Load event generated an interrupt.
0h = Event Cleared 1h = Event Set |
0 | Z | R | 0h | Zero event generated an interrupt.
0h = Event Cleared 1h = Event Set |
MIS is shown in Figure 25-54 and described in Table 25-41.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | |
28 | QEIERR | R | 0h | QEIERR
0h = Event Cleared 1h = Event Set |
27 | DC | R | 0h | Direction Change
0h = Event Cleared 1h = Event Set |
26 | REPC | R | 0h | Repeat Counter Zero
0h = Event Cleared 1h = Event Set |
25 | TOV | R | 0h | Trigger overflow
0h = Event Cleared 1h = Event Set |
24 | F | R | 0h | Fault
0h = Event Cleared 1h = Event Set |
23-16 | RESERVED | R | 0h | |
15 | CCU5 | R | 0h | Compare up event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
14 | CCU4 | R | 0h | Compare up event generated an interrupt CCP4
0h = Event Cleared 1h = Event Set |
13 | CCD5 | R | 0h | Compare down event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
12 | CCD4 | R | 0h | Compare down event generated an interrupt CCP4
0h = Event Cleared 1h = Event Set |
11 | CCU3 | R | 0h | Capture or compare up event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
10 | CCU2 | R | 0h | Capture or compare up event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
9 | CCU1 | R | 0h | Capture or compare up event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
8 | CCU0 | R | 0h | Capture or compare up event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
7 | CCD3 | R | 0h | Capture or compare down event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
6 | CCD2 | R | 0h | Capture or compare down event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
5 | CCD1 | R | 0h | Capture or compare down event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
4 | CCD0 | R | 0h | Capture or compare down event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
3-2 | RESERVED | R | 0h | |
1 | L | R | 0h | Load event generated an interrupt.
0h = Event Cleared 1h = Event Set |
0 | Z | R | 0h | Zero event generated an interrupt.
0h = Event Cleared 1h = Event Set |
ISET is shown in Figure 25-55 and described in Table 25-42.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | W | 0h | |
28 | QEIERR | W | 0h | QEIERR event SET
0h = Writing 0 has no effect. 1h = Event Set |
27 | DC | W | 0h | Direction Change event SET
0h = Writing 0 has no effect. 1h = Event Set |
26 | REPC | W | 0h | Repeat Counter Zero event SET
0h = Writing 0 has no effect. 1h = Event Set |
25 | TOV | W | 0h | Trigger Overflow event SET
0h = Writing 0 has no effect. 1h = Event Set |
24 | F | W | 0h | Fault event SET
0h = Writing 0 has no effect. 1h = Event Set |
23-16 | RESERVED | W | 0h | |
15 | CCU5 | W | 0h | Compare up event 5 SET
0h = Writing 0 has no effect. 1h = Event Set |
14 | CCU4 | W | 0h | Compare up event 4 SET
0h = Writing 0 has no effect. 1h = Event Set |
13 | CCD5 | W | 0h | Compare down event 5 SET
0h = Writing 0 has no effect. 1h = Event Set |
12 | CCD4 | W | 0h | Compare down event 4 SET
0h = Writing 0 has no effect. 1h = Event Set |
11 | CCU3 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
10 | CCU2 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
9 | CCU1 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
8 | CCU0 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
7 | CCD3 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
6 | CCD2 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
5 | CCD1 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
4 | CCD0 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
3-2 | RESERVED | W | 0h | |
1 | L | W | 0h | Load event SET
0h = Writing 0 has no effect. 1h = Event Set |
0 | Z | W | 0h | Zero event SET
0h = Writing 0 has no effect. 1h = Event Set |
ICLR is shown in Figure 25-56 and described in Table 25-43.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | W | 0h | |
28 | QEIERR | W | 0h | QEIERR event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
27 | DC | W | 0h | Direction Change event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
26 | REPC | W | 0h | Repeat Counter Zero event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
25 | TOV | W | 0h | Trigger Overflow event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
24 | F | W | 0h | Fault event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
23-16 | RESERVED | W | 0h | |
15 | CCU5 | W | 0h | Compare up event 5 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
14 | CCU4 | W | 0h | Compare up event 4 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
13 | CCD5 | W | 0h | Compare down event 5 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
12 | CCD4 | W | 0h | Compare down event 4 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
11 | CCU3 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
10 | CCU2 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
9 | CCU1 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
8 | CCU0 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
7 | CCD3 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
6 | CCD2 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
5 | CCD1 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
4 | CCD0 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
3-2 | RESERVED | W | 0h | |
1 | L | W | 0h | Load event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
0 | Z | W | 0h | Zero event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
IIDX is shown in Figure 25-57 and described in Table 25-44.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
00h = No interrupt pending 01h = Interrupt Source: Zero event (Z) 02h = nterrupt Source: Load event (L) 05h = Interrupt Source: Capture or compare down event (CCD0) 06h = Interrupt Source: Capture or compare down event (CCD1) 07h = Interrupt Source: Capture or compare down event (CCD2) 08h = Interrupt Source: Capture or compare down event (CCD3) 09h = Interrupt Source: Capture or compare up event (CCU0) 0Ah = Interrupt Source: Capture or compare up event (CCU1) 0Bh = Interrupt Source: Capture or compare up event (CCU2) 0Ch = Interrupt Source: Capture or compare up event (CCU3) 0Dh = Interrupt Source: Compare down event (CCD4) 0Eh = Interrupt Source: Compare down event (CCD5) 0Fh = Interrupt Source: Compare down event (CCU4) 10h = Interrupt Source: Compare down event (CCU5) 19h = Interrupt Source: Fault Event generated an interrupt. (F) 1Ah = Interrupt Source: Trigger overflow (TOV) 1Bh = Interrupt Source: Repeat Counter Zero (REPC) 1Ch = Interrupt Source: Direction Change (DC) 1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR) |
IMASK is shown in Figure 25-58 and described in Table 25-45.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W- | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | 0h | |
28 | QEIERR | R/W | 0h | QEIERR Event mask
0h = Disable Event 1h = Enable Event |
27 | DC | R/W | 0h | Direction Change Event mask
0h = Disable Event 1h = Enable Event |
26 | REPC | R/W | 0h | Repeat Counter Zero Event mask
0h = Disable Event 1h = Enable Event |
25 | TOV | R/W | 0h | Trigger Overflow Event mask
0h = Disable Event 1h = Enable Event |
24 | F | R/W | 0h | Fault Event mask
0h = Disable Event 1h = Enable Event |
23-16 | RESERVED | R/W | 0h | |
15 | CCU5 | R/W | 0h | Compare UP event mask CCP5
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
14 | CCU4 | R/W | 0h | Compare UP event mask CCP4
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
13 | CCD5 | R/W | 0h | Compare DN event mask CCP5
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
12 | CCD4 | R/W | 0h | Compare DN event mask CCP4
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
11 | CCU3 | R/W | 0h | Capture or Compare UP event mask CCP3
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
10 | CCU2 | R/W | 0h | Capture or Compare UP event mask CCP2
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9 | CCU1 | R/W | 0h | Capture or Compare UP event mask CCP1
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
8 | CCU0 | R/W | 0h | Capture or Compare UP event mask CCP0
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | CCD3 | R/W | 0h | Capture or Compare DN event mask CCP3
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | CCD2 | R/W | 0h | Capture or Compare DN event mask CCP2
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
5 | CCD1 | R/W | 0h | Capture or Compare DN event mask CCP1
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | CCD0 | R/W | 0h | Capture or Compare DN event mask CCP0
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3-2 | RESERVED | R/W | 0h | |
1 | L | R/W | 0h | Load Event mask
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | Z | R/W | 0h | Zero Event mask
0h = Disable Event 1h = Enable Event |
RIS is shown in Figure 25-59 and described in Table 25-46.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | |
28 | QEIERR | R | 0h | QEIERR, set on an incorrect state transition on the encoder interface.
0h = Event Cleared 1h = Event Set |
27 | DC | R | 0h | Direction Change
0h = Event Cleared 1h = Event Set |
26 | REPC | R | 0h | Repeat Counter Zero
0h = Event Cleared 1h = Event Set |
25 | TOV | R | 0h | Trigger overflow
0h = Event Cleared 1h = Event Set |
24 | F | R | 0h | Fault
0h = Event Cleared 1h = Event Set |
23-16 | RESERVED | R | 0h | |
15 | CCU5 | R | 0h | Compare up event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
14 | CCU4 | R | 0h | Compare up event generated an interrupt CCU4
0h = Event Cleared 1h = Event Set |
13 | CCD5 | R | 0h | Compare down event generated an interrupt CCD5
0h = Event Cleared 1h = Event Set |
12 | CCD4 | R | 0h | Compare down event generated an interrupt CCD4
0h = Event Cleared 1h = Event Set |
11 | CCU3 | R | 0h | Capture or compare up event generated an interrupt CCP3 0h = Event Cleared 1h = Event Set |
10 | CCU2 | R | 0h | Capture or compare up event generated an interrupt CCP2 0h = Event Cleared 1h = Event Set |
9 | CCU1 | R | 0h | Capture or compare up event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
8 | CCU0 | R | 0h | Capture or compare up event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
7 | CCD3 | R | 0h | Capture or compare down event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
6 | CCD2 | R | 0h | Capture or compare down event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
5 | CCD1 | R | 0h | Capture or compare down event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
4 | CCD0 | R | 0h | Capture or compare down event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
3-2 | RESERVED | R | 0h | |
1 | L | R | 0h | Load event generated an interrupt.
0h = Event Cleared 1h = Event Set |
0 | Z | R | 0h | Zero event generated an interrupt.
0h = Event Cleared 1h = Event Set |
MIS is shown in Figure 25-60 and described in Table 25-47.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | |
28 | QEIERR | R | 0h | QEIERR
0h = Event Cleared 1h = Event Set |
27 | DC | R | 0h | Direction Change
0h = Event Cleared 1h = Event Set |
26 | REPC | R | 0h | Repeat Counter Zero
0h = Event Cleared 1h = Event Set |
25 | TOV | R | 0h | Trigger overflow
0h = Event Cleared 1h = Event Set |
24 | F | R | 0h | Fault
0h = Event Cleared 1h = Event Set |
23-16 | RESERVED | R | 0h | |
15 | CCU5 | R | 0h | Compare up event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
14 | CCU4 | R | 0h | Compare up event generated an interrupt CCP4
0h = Event Cleared 1h = Event Set |
13 | CCD5 | R | 0h | Compare down event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
12 | CCD4 | R | 0h | Compare down event generated an interrupt CCP4
0h = Event Cleared 1h = Event Set |
11 | CCU3 | R | 0h | Capture or compare up event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
10 | CCU2 | R | 0h | Capture or compare up event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
9 | CCU1 | R | 0h | Capture or compare up event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
8 | CCU0 | R | 0h | Capture or compare up event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
7 | CCD3 | R | 0h | Capture or compare down event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
6 | CCD2 | R | 0h | Capture or compare down event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
5 | CCD1 | R | 0h | Capture or compare down event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
4 | CCD0 | R | 0h | Capture or compare down event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
3-2 | RESERVED | R | 0h | |
1 | L | R | 0h | Load event generated an interrupt.
0h = Event Cleared 1h = Event Set |
0 | Z | R | 0h | Zero event generated an interrupt.
0h = Event Cleared 1h = Event Set |
ISET is shown in Figure 25-61 and described in Table 25-48.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | W | 0h | |
28 | QEIERR | W | 0h | QEIERR event SET
0h = Writing 0 has no effect. 1h = Event Set |
27 | DC | W | 0h | Direction Change event SET
0h = Writing 0 has no effect. 1h = Event Set |
26 | REPC | W | 0h | Repeat Counter Zero event SET
0h = Writing 0 has no effect. 1h = Event Set |
25 | TOV | W | 0h | Trigger Overflow event SET
0h = Writing 0 has no effect. 1h = Event Set |
24 | F | W | 0h | Fault event SET
0h = Writing 0 has no effect. 1h = Event Set |
23-16 | RESERVED | W | 0h | |
15 | CCU5 | W | 0h | Compare up event 5 SET
0h = Writing 0 has no effect. 1h = Event Set |
14 | CCU4 | W | 0h | Compare up event 4 SET
0h = Writing 0 has no effect. 1h = Event Set |
13 | CCD5 | W | 0h | Compare down event 5 SET
0h = Writing 0 has no effect. 1h = Event Set |
12 | CCD4 | W | 0h | Compare down event 4 SET
0h = Writing 0 has no effect. 1h = Event Set |
11 | CCU3 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
10 | CCU2 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
9 | CCU1 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
8 | CCU0 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
7 | CCD3 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
6 | CCD2 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
5 | CCD1 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
4 | CCD0 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
3-2 | RESERVED | W | 0h | |
1 | L | W | 0h | Load event SET
0h = Writing 0 has no effect. 1h = Event Set |
0 | Z | W | 0h | Zero event SET
0h = Writing 0 has no effect. 1h = Event Set |
ICLR is shown in Figure 25-62 and described in Table 25-49.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | W | 0h | |
28 | QEIERR | W | 0h | QEIERR event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
27 | DC | W | 0h | Direction Change event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
26 | REPC | W | 0h | Repeat Counter Zero event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
25 | TOV | W | 0h | Trigger Overflow event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
24 | F | W | 0h | Fault event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
23-16 | RESERVED | W | 0h | |
15 | CCU5 | W | 0h | Compare up event 5 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
14 | CCU4 | W | 0h | Compare up event 4 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
13 | CCD5 | W | 0h | Compare down event 5 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
12 | CCD4 | W | 0h | Compare down event 4 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
11 | CCU3 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
10 | CCU2 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
9 | CCU1 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
8 | CCU0 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
7 | CCD3 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
6 | CCD2 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
5 | CCD1 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
4 | CCD0 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
3-2 | RESERVED | W | 0h | |
1 | L | W | 0h | Load event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
0 | Z | W | 0h | Zero event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
IIDX is shown in Figure 25-63 and described in Table 25-50.
Return to the Summary Table.
This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | Interrupt index status
00h = No interrupt pending 01h = Interrupt Source: Zero event (Z) 02h = nterrupt Source: Load event (L) 05h = Interrupt Source: Capture or compare down event (CCD0) 06h = Interrupt Source: Capture or compare down event (CCD1) 07h = Interrupt Source: Capture or compare down event (CCD2) 08h = Interrupt Source: Capture or compare down event (CCD3) 09h = Interrupt Source: Capture or compare up event (CCU0) 0Ah = Interrupt Source: Capture or compare up event (CCU1) 0Bh = Interrupt Source: Capture or compare up event (CCU2) 0Ch = Interrupt Source: Capture or compare up event (CCU3) 0Dh = Interrupt Source: Compare down event (CCD4) 0Eh = Interrupt Source: Compare down event (CCD5) 0Fh = Interrupt Source: Compare down event (CCU4) 10h = Interrupt Source: Compare down event (CCU5) 19h = Interrupt Source: Fault Event generated an interrupt. (F) 1Ah = Interrupt Source: Trigger overflow (TOV) 1Bh = Interrupt Source: Repeat Counter Zero (REPC) 1Ch = Interrupt Source: Direction Change (DC) 1Dh = Interrupt Source:QEI Incorrect state transition error (QEIERR) |
IMASK is shown in Figure 25-64 and described in Table 25-51.
Return to the Summary Table.
Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.”
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W- | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | 0h | |
28 | QEIERR | R/W | 0h | QEIERR Event mask
0h = Disable Event 1h = Enable Event |
27 | DC | R/W | 0h | Direction Change Event mask
0h = Disable Event 1h = Enable Event |
26 | REPC | R/W | 0h | Repeat Counter Zero Event mask
0h = Disable Event 1h = Enable Event |
25 | TOV | R/W | 0h | Trigger Overflow Event mask
0h = Disable Event 1h = Enable Event |
24 | F | R/W | 0h | Fault Event mask
0h = Disable Event 1h = Enable Event |
23-16 | RESERVED | R/W | 0h | |
15 | CCU5 | R/W | 0h | Compare UP event mask CCP5
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
14 | CCU4 | R/W | 0h | Compare UP event mask CCP4
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
13 | CCD5 | R/W | 0h | Compare DN event mask CCP5
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
12 | CCD4 | R/W | 0h | Compare DN event mask CCP4
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
11 | CCU3 | R/W | 0h | Capture or Compare UP event mask CCP3
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
10 | CCU2 | R/W | 0h | Capture or Compare UP event mask CCP2
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9 | CCU1 | R/W | 0h | Capture or Compare UP event mask CCP1
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
8 | CCU0 | R/W | 0h | Capture or Compare UP event mask CCP0
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | CCD3 | R/W | 0h | Capture or Compare DN event mask CCP3
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | CCD2 | R/W | 0h | Capture or Compare DN event mask CCP2
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
5 | CCD1 | R/W | 0h | Capture or Compare DN event mask CCP1
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | CCD0 | R/W | 0h | Capture or Compare DN event mask CCP0
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3-2 | RESERVED | R/W | 0h | |
1 | L | R/W | 0h | Load Event mask
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | Z | R/W | 0h | Zero Event mask
0h = Disable Event 1h = Enable Event |
RIS is shown in Figure 25-65 and described in Table 25-52.
Return to the Summary Table.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | |
28 | QEIERR | R | 0h | QEIERR, set on an incorrect state transition on the encoder interface.
0h = Event Cleared 1h = Event Set |
27 | DC | R | 0h | Direction Change
0h = Event Cleared 1h = Event Set |
26 | REPC | R | 0h | Repeat Counter Zero
0h = Event Cleared 1h = Event Set |
25 | TOV | R | 0h | Trigger overflow
0h = Event Cleared 1h = Event Set |
24 | F | R | 0h | Fault
0h = Event Cleared 1h = Event Set |
23-16 | RESERVED | R | 0h | |
15 | CCU5 | R | 0h | Compare up event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
14 | CCU4 | R | 0h | Compare up event generated an interrupt CCU4
0h = Event Cleared 1h = Event Set |
13 | CCD5 | R | 0h | Compare down event generated an interrupt CCD5
0h = Event Cleared 1h = Event Set |
12 | CCD4 | R | 0h | Compare down event generated an interrupt CCD4
0h = Event Cleared 1h = Event Set |
11 | CCU3 | R | 0h | Capture or compare up event generated an interrupt CCP3 0h = Event Cleared 1h = Event Set |
10 | CCU2 | R | 0h | Capture or compare up event generated an interrupt CCP2 0h = Event Cleared 1h = Event Set |
9 | CCU1 | R | 0h | Capture or compare up event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
8 | CCU0 | R | 0h | Capture or compare up event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
7 | CCD3 | R | 0h | Capture or compare down event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
6 | CCD2 | R | 0h | Capture or compare down event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
5 | CCD1 | R | 0h | Capture or compare down event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
4 | CCD0 | R | 0h | Capture or compare down event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
3-2 | RESERVED | R | 0h | |
1 | L | R | 0h | Load event generated an interrupt.
0h = Event Cleared 1h = Event Set |
0 | Z | R | 0h | Zero event generated an interrupt.
0h = Event Cleared 1h = Event Set |
MIS is shown in Figure 25-66 and described in Table 25-53.
Return to the Summary Table.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | |
28 | QEIERR | R | 0h | QEIERR
0h = Event Cleared 1h = Event Set |
27 | DC | R | 0h | Direction Change
0h = Event Cleared 1h = Event Set |
26 | REPC | R | 0h | Repeat Counter Zero
0h = Event Cleared 1h = Event Set |
25 | TOV | R | 0h | Trigger overflow
0h = Event Cleared 1h = Event Set |
24 | F | R | 0h | Fault
0h = Event Cleared 1h = Event Set |
23-16 | RESERVED | R | 0h | |
15 | CCU5 | R | 0h | Compare up event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
14 | CCU4 | R | 0h | Compare up event generated an interrupt CCP4
0h = Event Cleared 1h = Event Set |
13 | CCD5 | R | 0h | Compare down event generated an interrupt CCP5
0h = Event Cleared 1h = Event Set |
12 | CCD4 | R | 0h | Compare down event generated an interrupt CCP4
0h = Event Cleared 1h = Event Set |
11 | CCU3 | R | 0h | Capture or compare up event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
10 | CCU2 | R | 0h | Capture or compare up event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
9 | CCU1 | R | 0h | Capture or compare up event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
8 | CCU0 | R | 0h | Capture or compare up event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
7 | CCD3 | R | 0h | Capture or compare down event generated an interrupt CCP3
0h = Event Cleared 1h = Event Set |
6 | CCD2 | R | 0h | Capture or compare down event generated an interrupt CCP2
0h = Event Cleared 1h = Event Set |
5 | CCD1 | R | 0h | Capture or compare down event generated an interrupt CCP1
0h = Event Cleared 1h = Event Set |
4 | CCD0 | R | 0h | Capture or compare down event generated an interrupt CCP0
0h = Event Cleared 1h = Event Set |
3-2 | RESERVED | R | 0h | |
1 | L | R | 0h | Load event generated an interrupt.
0h = Event Cleared 1h = Event Set |
0 | Z | R | 0h | Zero event generated an interrupt.
0h = Event Cleared 1h = Event Set |
ISET is shown in Figure 25-67 and described in Table 25-54.
Return to the Summary Table.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | W | 0h | |
28 | QEIERR | W | 0h | QEIERR event SET
0h = Writing 0 has no effect. 1h = Event Set |
27 | DC | W | 0h | Direction Change event SET
0h = Writing 0 has no effect. 1h = Event Set |
26 | REPC | W | 0h | Repeat Counter Zero event SET
0h = Writing 0 has no effect. 1h = Event Set |
25 | TOV | W | 0h | Trigger Overflow event SET
0h = Writing 0 has no effect. 1h = Event Set |
24 | F | W | 0h | Fault event SET
0h = Writing 0 has no effect. 1h = Event Set |
23-16 | RESERVED | W | 0h | |
15 | CCU5 | W | 0h | Compare up event 5 SET
0h = Writing 0 has no effect. 1h = Event Set |
14 | CCU4 | W | 0h | Compare up event 4 SET
0h = Writing 0 has no effect. 1h = Event Set |
13 | CCD5 | W | 0h | Compare down event 5 SET
0h = Writing 0 has no effect. 1h = Event Set |
12 | CCD4 | W | 0h | Compare down event 4 SET
0h = Writing 0 has no effect. 1h = Event Set |
11 | CCU3 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
10 | CCU2 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
9 | CCU1 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
8 | CCU0 | W | 0h | Capture or compare up event SET
0h = Writing 0 has no effect. 1h = Event Set |
7 | CCD3 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
6 | CCD2 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
5 | CCD1 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
4 | CCD0 | W | 0h | Capture or compare down event SET
0h = Writing 0 has no effect. 1h = Event Set |
3-2 | RESERVED | W | 0h | |
1 | L | W | 0h | Load event SET
0h = Writing 0 has no effect. 1h = Event Set |
0 | Z | W | 0h | Zero event SET
0h = Writing 0 has no effect. 1h = Event Set |
ICLR is shown in Figure 25-68 and described in Table 25-55.
Return to the Summary Table.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | QEIERR | DC | REPC | TOV | F | ||
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCU5 | CCU4 | CCD5 | CCD4 | CCU3 | CCU2 | CCU1 | CCU0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD3 | CCD2 | CCD1 | CCD0 | RESERVED | L | Z | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | W | 0h | |
28 | QEIERR | W | 0h | QEIERR event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
27 | DC | W | 0h | Direction Change event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
26 | REPC | W | 0h | Repeat Counter Zero event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
25 | TOV | W | 0h | Trigger Overflow event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
24 | F | W | 0h | Fault event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
23-16 | RESERVED | W | 0h | |
15 | CCU5 | W | 0h | Compare up event 5 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
14 | CCU4 | W | 0h | Compare up event 4 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
13 | CCD5 | W | 0h | Compare down event 5 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
12 | CCD4 | W | 0h | Compare down event 4 CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
11 | CCU3 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
10 | CCU2 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
9 | CCU1 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
8 | CCU0 | W | 0h | Capture or compare up event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
7 | CCD3 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
6 | CCD2 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
5 | CCD1 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
4 | CCD0 | W | 0h | Capture or compare down event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
3-2 | RESERVED | W | 0h | |
1 | L | W | 0h | Load event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
0 | Z | W | 0h | Zero event CLEAR
0h = Writing 0 has no effect. 1h = Event Clear |
EVT_MODE is shown in Figure 25-69 and described in Table 25-56.
Return to the Summary Table.
Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT2_CFG | EVT1_CFG | EVT0_CFG | ||||
R/W-0h | R-2h | R-2h | R-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5-4 | EVT2_CFG | R | 2h | Event line mode select for event corresponding to GEN_EVENT1
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
3-2 | EVT1_CFG | R | 2h | Event line mode select for event corresponding to GEN_EVENT0
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | EVT0_CFG | R | 1h | Event line mode select for event corresponding to CPU_INT
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
DESC is shown in Figure 25-70 and described in Table 25-57.
Return to the Summary Table.
This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R-1111h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | INSTNUM | MAJREV | MINREV | ||||||||||||
R- | R- | R- | R- | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 1111h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness.
0h = Smallest value FFFFh = Highest possible value |
15-12 | FEATUREVER | R | 0h | Feature Set for the module *instance*
0h = Smallest value Fh = Highest possible value |
11-8 | INSTNUM | R | 0h | Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances
0h = Smallest value Fh = Highest possible value |
7-4 | MAJREV | R | 0h | Major rev of the IP
0h = Smallest value Fh = Highest possible value |
3-0 | MINREV | R | 0h | Minor rev of the IP
0h = Smallest value Fh = Highest possible value |
CCPD is shown in Figure 25-71 and described in Table 25-58.
Return to the Summary Table.
CCP Direction. Controls whether CCP is used as an input or an output.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | C0CCP3 | C0CCP2 | C0CCP1 | C0CCP0 | |||
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | C0CCP3 | R/W | 0h | CCP3 direction
0h = Input 1h = Output |
2 | C0CCP2 | R/W | 0h | CCP2 direction
0h = input 1h = Output |
1 | C0CCP1 | R/W | 0h | CCP1 direction
0h = Input 1h = Output |
0 | C0CCP0 | R/W | 0h | CCP0 direction
0h = Input 1h = Output |
ODIS is shown in Figure 25-72 and described in Table 25-59.
Return to the Summary Table.
The ODIS register output is inverted and then ANDed with the output signal selected by the OCTL register CCPO field (before conditional inversion) to allow software the ability to hold the CCP output low during configuration or shutdown.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | C0CCP3 | C0CCP2 | C0CCP1 | C0CCP0 | |||
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | |
3 | C0CCP3 | R/W | 0h | Counter CCP3 Disable Mask Defines whether CCP3 of Counter n is forced low or not 0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block. 1h = CCP output is forced low. |
2 | C0CCP2 | R/W | 0h | Counter CCP2 Disable Mask Defines whether CCP2 of Counter n is forced low or not 0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block. 1h = CCP output is forced low. |
1 | C0CCP1 | R/W | 0h | Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block. 1h = CCP output is forced low. |
0 | C0CCP0 | R/W | 0h | Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not 0h = Output function as selected by the OCTL register CCPO field are provided to output inversion block. 1h = CCP output is forced low. |
CCLKCTL is shown in Figure 25-73 and described in Table 25-60.
Return to the Summary Table.
The CCLKCTL register provides a SW mechanism for gating the TIMER clock
if the module is expected not to be used but the power domain is alive.
This effectively puts the IP in an IDLE state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKEN | ||||||
R/W- | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | |
0 | CLKEN | R/W | 0h | Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock. 0h = Clock is disabled. 1h = Clock is enabled |
CPS is shown in Figure 25-74 and described in Table 25-61.
Return to the Summary Table.
The CPS register provides the value for the clock pre-scaler.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PCNT | ||||||||||||||||||||||||||||||
R/W- | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | PCNT | R/W | 0h | Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock 0h = Minimum value FFh = Maximum Value |
CPSV is shown in Figure 25-75 and described in Table 25-62.
Return to the Summary Table.
The CPSV register provides the ability to read the current clock prescale count value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPSVAL | ||||||||||||||||||||||||||||||
R- | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | CPSVAL | R | 0h | Current Prescale Count Value
0h = Minimum value FFh = Maximum Value |
CTTRIGCTL is shown in Figure 25-76 and described in Table 25-63.
Return to the Summary Table.
Cross Timer Trigger Control Register
This register is used to control the cross trigger connections for enables and faults of different timer instances in the same power domain. Please refer to sections Timer Module Cross Trigger (In/Out) and Fault Cross Triggering for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EVTCTTRIGSEL | ||||||
R/W- | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVTCTEN | CTEN | |||||
R/W- | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | 0h | |
19-16 | EVTCTTRIGSEL | R/W | 0h | Used to Select the subscriber port that should be used for input cross trigger.
0h = Use FSUB0 as cross trigger source. 1h = Use FSUB1 as cross trigger source. 2h = Use Zero event as cross trigger source. 3h = Use Load event as cross trigger source. 4h = Use CCD0 event as cross trigger source. 5h = Use CCD1 event as cross trigger source. 6h = Use CCD2 event as cross trigger source. 7h = Use CCD3 event as cross trigger source. 8h = Use CCU0 event as cross trigger source. 9h = Use CCU1 event as cross trigger source. Ah = Use CCU2 event as cross trigger source. Bh = Use CCU3 event as cross trigger source. |
15-2 | RESERVED | R/W | 0h | |
1 | EVTCTEN | R/W | 0h | Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers.
0h = Cross trigger generation disabled. 1h = Cross trigger generation enabled |
0 | CTEN | R/W | 0h | Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register. 0h = Cross trigger generation disabled. 1h = Cross trigger generation enabled |
CTTRIG is shown in Figure 25-77 and described in Table 25-64.
Return to the Summary Table.
Cross Timer Trigger Register
This register is used to trigger the timer instances connected and enabled using CTTRIGCTL and CTTRIGMSK registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRIG | ||||||
W- | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | 0h | |
0 | TRIG | W | 0h | Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance. 0h = Cross trigger generation disabled 1h = Generate Cross trigger pulse |
FSCTL is shown in Figure 25-78 and described in Table 25-65.
Return to the Summary Table.
The FSCTL register controls the fault source selection and enable. There are 5 input fault sources either through synchronous path processing or asynchronous path.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FEX2EN | FEX1EN | FEX0EN | FAC2EN | FAC1EN | FAC0EN | FCEN |
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | 0h | |
6 | FEX2EN | R/W | 0h | This field controls whether the fault is caused by external fault pin 2.
0h = Disable 1h = Enable |
5 | FEX1EN | R/W | 0h | This field controls whether the fault is caused by external fault pin 1.
0h = Disable 1h = Enable |
4 | FEX0EN | R/W | 0h | This field controls whether the fault is caused by external fault pin 0.
0h = Disable 1h = Enable |
3 | FAC2EN | R/W | 0h | This field controls whether the fault is caused by COMP2 output.
0h = Disable 1h = Enable |
2 | FAC1EN | R/W | 0h | This field controls whether the fault is caused by COMP1 output.
0h = Disable 1h = Enable |
1 | FAC0EN | R/W | 0h | This field controls whether the fault signal is caused by COMP0 output.
0h = Disable 1h = Enable |
0 | FCEN | R/W | 0h | This field controls whether the fault is caused by the system clock fault.
0h = Disable 1h = Enable |
GCTL is shown in Figure 25-79 and described in Table 25-66.
Return to the Summary Table.
Global control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SHDWLDEN | ||||||
R/W- | R/W-1h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | |
0 | SHDWLDEN | R/W | 1h | Enables shadow to active load of bufferred registers and register fields.
0h = Disable 1h = Enable |
CTR is shown in Figure 25-80 and described in Table 25-67.
Return to the Summary Table.
This is the TIMER counter register.
This can be set by SW. However, the writes will be unpredictable if the software
tries to set a value while the counter is running.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCTR | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | CCTR | R/W | 0h | Current Counter value
0h = Minimum value 00FFFFFFh = Maximum Value |
CTRCTL is shown in Figure 25-81 and described in Table 25-68.
Return to the Summary Table.
This register provides control over the counter operation.
The configuration can change as well as setting the EN bit in a single write.
There is no requirement to change the configuration first and then do an
additional write to set the EN bit.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CVAE | RESERVED | PLEN | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SLZERCNEZ | RESERVED | FRB | FB | DRB | RESERVED | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CZC | CAC | CLC | |||||
R/W-7h | R/W-7h | R/W-7h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLC | RESERVED | CM | REPEAT | EN | |||
R/W-7h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | |
29-28 | CVAE | R/W | 0h | Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.
0h = The counter is set to the LOAD register value 1h = The counter value is unchanged from its current value which could have been initialized by software 2h = The counter is set to zero |
27-25 | RESERVED | R/W | 0h | |
24 | PLEN | R/W | 0h | Phase Load Enable. This bit allows the timer to have phase load feature. 0h = Disabled 1h = Enabled |
23 | SLZERCNEZ | R/W | 0h | Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero. This bit suppresses the generation of the Z (zero) and L (load) events from the counter when the repeat counter (RC) value is not 0. 0h = Disabled. Z and L events are always generated from the counter when their conditions are generated. 1h = Enabled. Z and L events are generated from the counter when their conditions are generated and the RC register value is 0. |
22-20 | RESERVED | R/W | 0h | |
19 | FRB | R/W | 0h | Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition.
0h = Resume counting 1h = Perform the action as specified by the CVAE field. |
18 | FB | R/W | 0h | Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0
0h = Continues counting 1h = Suspends counting |
17 | DRB | R/W | 0h | Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.
0h = Resume counting 1h = Perform the action as specified by the CVAE field. |
16 | RESERVED | R/W | 0h | |
15-13 | CZC | R/W | 7h | Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0h = CCCTL_0 ZCOND 1h = CCCTL_1 ZCOND 2h = CCCTL_2 ZCOND This value exists when there are 4 channels. 3h = CCCTL_3 ZCOND This value exists when there are 4 channels. 4h = Controlled by 2-input QEI mode This value exists when TIMER support QEI feature. 5h = Controlled by 3-input QEI mode This value exists when TIMER support QEI feature. |
12-10 | CAC | R/W | 7h | Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0h = CCCTL_0 ACOND 1h = CCCTL_1 ACOND 2h = CCCTL_2 ACOND This value exists when there are 4 channels. 3h = CCCTL_3 ACOND This value exists when there are 4 channels. 4h = Controlled by 2-input QEI mode This value exists when TIMER support QEI feature. 5h = Controlled by 3-input QEI mode This value exists when TIMER support QEI feature. |
9-7 | CLC | R/W | 7h | Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved. 0h = CCCTL_0 LCOND 1h = CCCTL_1 LCOND 2h = CCCTL_2 LCOND This value exists when there are 4 channels. 3h = CCCTL_3 LCOND This value exists when there are 4 channels. 4h = Controlled by 2 input QEI mode. This value exists when TIMER support QEI feature. 5h = Controlled by 3 input QEI mode. This value exists when TIMER support QEI feature. |
6 | RESERVED | R/W | 0h | |
5-4 | CM | R/W | 0h | Count Mode
0h = Down 1h = Up/Down 2h = Counter counts up. |
3-1 | REPEAT | R/W | 0h | Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.
0h = Does not automatically advance following a zero event. 1h = Continues to advance following a zero event. 2h = Reserved 3h = Continues to advance following a zero event if the debug mode is not in effect, or following the release of the debug mode. 4h = Reserved |
0 | EN | R/W | 0h | Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.
0h = Disabled 1h = Enabled |
LOAD is shown in Figure 25-82 and described in Table 25-69.
Return to the Summary Table.
The contents of LOAD register are copied to CTR on any operation designated to do a "LOAD". The LOAD is used to compare with the CTR for generating a "Load Event" that can be used for interrupt, trigger, or signal generator actions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LD | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | LD | R/W | 0h | Load Value
0h = Minimum value 00FFFFFFh = Maximum Value |
CC_01[y] is shown in Figure 25-83 and described in Table 25-70.
Return to the Summary Table.
The CC_01 register is a register that can be used as either a capture register, to capture the next CTR value on an event, or a compare to the current CTR to create an event. It cannot operate concurrently as both. There are two Capture-Compare slices of hardware for each counter, hence there are two CC_01 registers per timer. On a capture event, the next value of the CTR is loaded so that CTR and CC_01 (which captured) will be equal on the cycle that an interrupt or trigger is created from the capture action.
Offset = 1810h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCVAL | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | CCVAL | R/W | 0h | Capture or compare value
0h = Minimum value FFFFh = Maximum Value |
CC_23[y] is shown in Figure 25-84 and described in Table 25-71.
Return to the Summary Table.
The CC_23 register is a register that can be used as either a capture register, to capture the next CTR value on an event, or a compare to the current CTR to create an event. It cannot operate concurrently as both. There are two Capture-Compare slices of hardware for each counter, hence there are two CC_01 registers per timer. On a capture event, the next value of the CTR is loaded so that CTR and CC_01 (which captured) will be equal on the cycle that an interrupt or trigger is created from the capture action.
Offset = 1818h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCVAL | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | CCVAL | R/W | 0h | Capture or compare value
0h = Minimum value FFFFh = Maximum Value |
CC_45[y] is shown in Figure 25-85 and described in Table 25-72.
Return to the Summary Table.
The CC_45 register are a registers which can be used as compare to the current CTR to create an events CC4U, CC4D, CC5U and CC5D.
Offset = 1820h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCVAL | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | CCVAL | R/W | 0h | Capture or compare value
0h = Minimum value FFFFh = Maximum Value |
CCCTL_01[y] is shown in Figure 25-86 and described in Table 25-73.
Return to the Summary Table.
The CCCTL_01 registers control the operations of the respective CC registers and the counter.
Offset = 1830h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CC2SELD | CCACTUPD | SCERCNEZ | CC2SELU | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CC2SELU | RESERVED | CCUPD | COC | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ZCOND | RESERVED | LCOND | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACOND | RESERVED | CCOND | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | CC2SELD | R/W | 0h | Selects the source second CCD event.
0h = Selects CCD from CC0. 1h = Selects CCD from CC1. 2h = Selects CCD from CC2. 3h = Selects CCD from CC3. 4h = Selects CCD from CC4. 5h = Selects CCD from CC5. |
28-26 | CCACTUPD | R/W | 0h | CCACT shadow register Update Method This field controls how updates to the CCACT shadow register are performed 0h = Value written to the CCACT register has immediate effect. 1h = Following a zero event (CTR=0) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 2h = Following a CCD event (CTR=CC_xy) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 3h = Following a CCU event (CTR=CC_xy) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 4h = Following a zero event (CTR=0) or load event (CTR = LOAD) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 5h = Following a zero event (CTR=0) with repeat count also zero (RC=0). Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 6h = On a TRIG pulse, the value stored in CCACT_xy shadow register is loaded into CCACT_xy register. |
25 | SCERCNEZ | R/W | 0h | Suppress Compare Event if Repeat Counter is Not Equal to Zero This bit suppresses the generation of the compare (CCD, CCU and RC) events from the counter when the repeat counter (RC) value is not 0. 0h = CCD, CCU and RC events are always generated from the counter when their conditions are generated. 1h = CCD, CCU and RC events are generated from the counter when their conditions are generated and the RC register value is 0. |
24-22 | CC2SELU | R/W | 0h | Selects the source second CCU event.
0h = Selects CCU from CC0. 1h = Selects CCU from CC1. 2h = Selects CCU from CC2. 3h = Selects CCU from CC3. 4h = Selects CCU from CC4. 5h = Selects CCU from CC5. |
21 | RESERVED | R/W | 0h | |
20-18 | CCUPD | R/W | 0h | Capture and Compare Update Method This field controls how updates to the shadow capture and compare register are performed (when operating in compare mode, COC=0). 0h = Writes to the CCx_y register is written to the register directly and has immediate effect. 1h = Following a zero event (CTR=0) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 2h = Following a CCD event (CTR=CC_xy) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 3h = Following a CCU event (CTR=CC_xy) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 4h = Following a zero event(CTR=0) or load event (CTR=LOAD) Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 5h = Following a zero event (CTR=0) with repeat count also zero (RC=0). Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 6h = Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y |
17 | COC | R/W | 0h | Capture or Compare. Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0h = Compare 1h = Capture |
16-15 | RESERVED | R/W | 0h | |
14-12 | ZCOND | R/W | 0h | Zero Condition. This field specifies the condition that generates a zero pulse. 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) |
11 | RESERVED | R/W | 0h | |
10-8 | LCOND | R/W | 0h | Load Condition. Specifies the condition that generates a load pulse. 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) |
7 | RESERVED | R/W | 0h | |
6-4 | ACOND | R/W | 0h | Advance Condition. Specifies the condition that generates an advance pulse. 0h = Each TIMCLK 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) 5h = CCP High or Trigger assertion (level) |
3 | RESERVED | R/W | 0h | |
2-0 | CCOND | R/W | 0h | Capture Condition. Specifies the condition that generates a capture pulse. 0h = None (never captures) 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) |
CCCTL_23[y] is shown in Figure 25-87 and described in Table 25-74.
Return to the Summary Table.
The CCCTL registers control the operations of the respective CC registers and the counter.
Offset = 1838h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CC2SELD | CCACTUPD | SCERCNEZ | CC2SELU | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CC2SELU | RESERVED | CCUPD | COC | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ZCOND | RESERVED | LCOND | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ACOND | RESERVED | CCOND | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | CC2SELD | R/W | 0h | Selects the source second CCD event.
0h = Selects CCD from CC0. 1h = Selects CCD from CC1. 2h = Selects CCD from CC2. 3h = Selects CCD from CC3. 4h = Selects CCD from CC4. 5h = Selects CCD from CC5. |
28-26 | CCACTUPD | R/W | 0h | CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed 0h = Value written to the CCACTx_y register has immediate effect. 1h = Following a zero event (CTR=0) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0. 2h = Following a CCD event (CTR=CC_xy) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 3h = Following a CCU event (CTR=cc_xy) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 4h = Following a zero event (CTR=0) or load event (CTR=LOAD) Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 5h = Following a zero event (CTR=0) with repeat count also zero (RC=0). Writes to the CCACTx_y register are stored in shadow register and transferred to CCACTx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 6h = On a TRIG pulse, the value stored in CCACTx_y shadow register is loaded into CCACTx_y active register. |
25 | SCERCNEZ | R/W | 0h | Suppress Compare Event if Repeat Counter is Not Equal to Zero This bit suppresses the generation of the compare (CCD, CCU and RC) events from the counter when the repeat counter (RCn) value is not 0. 0h = CCD, CCU and RC events are always generated from the counter when their conditions are generated. 1h = CCD, CCU and RC events are generated from the counter when their conditions are generated and the RC register value is 0. |
24-22 | CC2SELU | R/W | 0h | Selects the source second CCU event.
0h = Selects CCU from CC0. 1h = Selects CCU from CC1. 2h = Selects CCU from CC2. 3h = Selects CCU from CC3. 4h = Selects CCU from CC4. 5h = Selects CCU from CC5. |
21 | RESERVED | R/W | 0h | |
20-18 | CCUPD | R/W | 0h | Capture and Compare Update Method This field controls how updates to the shadow capture and compare register are performed (when operating in compare mode, COC=0). 0h = Writes to the CCx_y register is written to the register directly and has immediate effect. 1h = Following a zero event (CTR=0) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0. 2h = Following a CCD event (CTR=CC_xy) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 3h = Following a CCU event (CTR=CC_xy) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 4h = Following a zero or load event Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LDn. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 5h = Following a zero event (CTR=0) with repeat count also zero (RC=0). Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 6h = Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. |
17 | COC | R/W | 0h | Capture or Compare. Specifies whether the corresponding CC register is used as a capture register or a compare register (never both). 0h = Compare 1h = Capture |
16-15 | RESERVED | R/W | 0h | |
14-12 | ZCOND | R/W | 0h | Zero Condition. This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) |
11 | RESERVED | R/W | 0h | |
10-8 | LCOND | R/W | 0h | Load Condition. Specifies the condition that generates a load pulse. 4h-Fh = Reserved 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) |
7 | RESERVED | R/W | 0h | |
6-4 | ACOND | R/W | 0h | Advance Condition. Specifies the condition that generates an advance pulse. 6h-Fh = Reserved 0h = Each TIMCLK 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) 5h = CCP High or Trigger assertion (level) |
3 | RESERVED | R/W | 0h | |
2-0 | CCOND | R/W | 0h | Capture Condition. Specifies the condition that generates a capture pulse. 4h-Fh = Reserved 0h = None (never captures) 1h = Rising edge of CCP or trigger assertion edge 2h = Falling edge of CCP or trigger de-assertion edge 3h = Either edge of CCP or trigger change (assertion/de-assertion edge) |
CCCTL_45[y] is shown in Figure 25-88 and described in Table 25-75.
Return to the Summary Table.
The CCCTL registers control the operations of the respective CC registers and the counter.
Offset = 1840h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SCERCNEZ | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CCUPD | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | 0h | |
25 | SCERCNEZ | R/W | 0h | Suppress Compare Event if Repeat Counter is Not Equal to Zero This bit suppresses the generation of the compare (CCD, CCU and RC) events from the counter when the repeat counter (RC) value is not 0. 0h = CCD, CCU and RC events are always generated from the counter when their conditions are generated. 1h = CCD, CCU and RC events are generated from the counter when their conditions are generated and the RC register value is 0. |
24-21 | RESERVED | R/W | 0h | |
20-18 | CCUPD | R/W | 0h | Capture and Compare Update Method This field controls how updates to the shadow capture and compare register are performed (when operating in compare mode, COC=0). 0h = Writes to the CCx_y register is written to the register directly and has immediate effect. 1h = Following a zero event (CTR=0) Writes to the CCx_y register are stored in shadow register and transferred to ECCx_y in the TIMCLK cycle following CTR equals 0. 2h = Following a CCD event (CTR=CC_xy) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 3h = Following a CCU event (CTR=CC_xy) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals the CCx_y register value. 4h = Following a zero event (CTR=0) or load event (CTR=LOAD) Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 or CTR. Equals LD. Note this update mechanism is defined for use only in configurations using up/down counting. This mode is not intended for use in down count configurations. 5h = Following a zero event (CTR=0) with repeat count also zero (RC=0). Writes to the CCx_y register are stored in shadow register and transferred to CCx_y in the TIMCLK cycle following CTR equals 0 and if RC equal 0. 6h = Following a TRIG pulse. Writes to the CCx_y register are stored in shadow register and transferred to CCx_y #xD; 0. |
17-0 | RESERVED | R/W | 0h |
OCTL_01[y] is shown in Figure 25-89 and described in Table 25-76.
Return to the Summary Table.
The OCTL_01 register controls the CCP output of the Capture-Compare slice of the counter. This includes the ability to select the source of what is driven out along with initial condition values and final inversion options.
Offset = 1850h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCPIV | CCPOINV | CCPO | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5 | CCPIV | R/W | 0h | CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0h = Low 1h = High |
4 | CCPOINV | R/W | 0h | CCP Output Invert The output as selected by CCPO is conditionally inverted.
0h = No inversion 1h = Invert |
3-0 | CCPO | R/W | 0h | CCP Output Source
0h = Signal generator value (for example, PWM, triggered PWM) 1h = Load event 2h = CCU event or CCD event 4h = Zero event 5h = Capture event 6h = Fault condition 8h = Mirror CCP of first capture and compare register to other capture compare blocks 9h = Mirror CCP of second capture and compare register in other capture compare blocks Ch = Signal generator output after deadband insertion Dh = Counter direction |
OCTL_23[y] is shown in Figure 25-90 and described in Table 25-77.
Return to the Summary Table.
The OCTL register controls the CCP output of the Capture-Compare slice of the counter. This includes the ability to select the source of what is driven out along with initial condition values and final inversion options.
Offset = 1858h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCPIV | CCPOINV | CCPO | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | |
5 | CCPIV | R/W | 0h | CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).
0h = Low 1h = High |
4 | CCPOINV | R/W | 0h | CCP Output Invert The output as selected by CCPO is conditionally inverted.
0h = No inversion 1h = Invert |
3-0 | CCPO | R/W | 0h | CCP Output Source
0h = Signal generator value (for example, PWM, triggered PWM) 1h = Load condition 2h = CCU event or CCD event 4h = Zero event 5h = Capture event 6h = Fault Condition 8h = Mirror CCP of first capture and compare register in other capture compare blocks 9h = Mirror CCP of second capture and compare register in other capture compare blocksi /bn,. Ch = Deadband Inserted Output Dh = Counter direction |
CCACT_01[y] is shown in Figure 25-91 and described in Table 25-78.
Return to the Summary Table.
The CCACT_01 register controls the actions of the signal generator of the capture-compare slice based on the events created in the counter block, the capture and compare block and debug events.
Offset = 1870h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SWFRCACT_CMPL | SWFRCACT | FEXACT | FENACT | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FENACT | RESERVED | CC2UACT | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CC2UACT | RESERVED | CC2DACT | RESERVED | CUACT | RESERVED | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CDACT | RESERVED | LACT | RESERVED | ZACT | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SWFRCACT_CMPL | R/W | 0h | CCP Complimentary output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP Complimentary output value is set high 2h = CCP Complimentary output value is set low |
29-28 | SWFRCACT | R/W | 0h | CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low |
27-25 | FEXACT | R/W | 0h | CCP Output Action on Fault Exit This field describes the resulting action of the signal generator upon exiting the fault condition. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled 4h = CCP output value is tristated |
24-22 | FENACT | R/W | 0h | CCP Output Action on Fault Entry This field describes the resulting action of the signal generator upon detecting a fault. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled 4h = CCP output value is tristated |
21-17 | RESERVED | R/W | 0h | |
16-15 | CC2UACT | R/W | 0h | CCP Output Action on CC2U event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
14 | RESERVED | R/W | 0h | |
13-12 | CC2DACT | R/W | 0h | CCP Output Action on CC2D event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
11 | RESERVED | R/W | 0h | |
10-9 | CUACT | R/W | 0h | CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
8 | RESERVED | R/W | 0h | |
7-6 | CDACT | R/W | 0h | CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
5 | RESERVED | R/W | 0h | |
4-3 | LACT | R/W | 0h | CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
2 | RESERVED | R/W | 0h | |
1-0 | ZACT | R/W | 0h | CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
CCACT_23[y] is shown in Figure 25-92 and described in Table 25-79.
Return to the Summary Table.
The CCACT register controls the actions of the signal generator of the capture-compare slice based on the events created in the counter block, the capture and compare block and debug events.
Offset = 1878h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SWFRCACT_CMPL | SWFRCACT | FEXACT | FENACT | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FENACT | RESERVED | CC2UACT | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CC2UACT | RESERVED | CC2DACT | RESERVED | CUACT | RESERVED | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CDACT | RESERVED | LACT | RESERVED | ZACT | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SWFRCACT_CMPL | R/W | 0h | CCP Complimentary Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP Complimentary output value is set high 2h = CCP Complimentary output value is set low |
29-28 | SWFRCACT | R/W | 0h | CCP Output Action on Software Force Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low |
27-25 | FEXACT | R/W | 0h | CCP Output Action on Fault Exit This field describes the resulting action of the signal generator upon exiting the fault condition. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled 4h = CCP output value is tristated |
24-22 | FENACT | R/W | 0h | CCP Output Action on Fault Entry This field describes the resulting action of the signal generator upon detecting a fault. 0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled 4h = CCP output value is tristated |
21-17 | RESERVED | R/W | 0h | |
16-15 | CC2UACT | R/W | 0h | CCP Output Action on CC2U event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
14 | RESERVED | R/W | 0h | |
13-12 | CC2DACT | R/W | 0h | CCP Output Action on CC2D event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
11 | RESERVED | R/W | 0h | |
10-9 | CUACT | R/W | 0h | CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
8 | RESERVED | R/W | 0h | |
7-6 | CDACT | R/W | 0h | CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
5 | RESERVED | R/W | 0h | |
4-3 | LACT | R/W | 0h | CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
2 | RESERVED | R/W | 0h | |
1-0 | ZACT | R/W | 0h | CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.
0h = This event is disabled and a lower priority event is selected if asserting. The CCP output value is unaffected by the event. 1h = CCP output value is set high 2h = CCP output value is set low 3h = CCP output value is toggled |
IFCTL_01[y] is shown in Figure 25-93 and described in Table 25-80.
Return to the Summary Table.
The IFCTL_01 register controls the input selection and inversion for the associated Capture-Compare slice.
Offset = 1880h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FE | CPV | RESERVED | FP | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INV | RESERVED | ISEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | 0h | |
12 | FE | R/W | 0h | Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0h = Bypass. 1h = Filtered. |
11 | CPV | R/W | 0h | Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0h = Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 1h = Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. |
10 | RESERVED | R/W | 0h | |
9-8 | FP | R/W | 0h | Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0h = The division factor is 3 1h = The division factor is 5 2h = The division factor is 8 |
7 | INV | R/W | 0h | Input Inversion This bit controls whether the selected input is inverted.
0h = Noninverted 1h = Inverted |
6-4 | RESERVED | R/W | 0h | |
3-0 | ISEL | R/W | 0h | Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0h = CCP of the corresponding capture compare unit 1h = Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 2h = CCP0 of the counter 3h = Trigger 4h = XOR of CCP inputs as input source (Used in Hall input mode). 5h = subscriber 0 event as input source. 6h = subscriber 1 event as input source. 7h = Comparator 0 output. 8h = Comparator 1 output. 9h = Comparator 2 output. |
IFCTL_23[y] is shown in Figure 25-94 and described in Table 25-81.
Return to the Summary Table.
The IFCTL register controls the input selection and inversion for the associated Capture-Compare slice.
Offset = 1888h + (y * 4h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FE | CPV | RESERVED | FP | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INV | RESERVED | ISEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | 0h | |
12 | FE | R/W | 0h | Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect. 0h = Bypass. 1h = Filtered. |
11 | CPV | R/W | 0h | Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0h = Consecutive Periods The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 1h = Voting The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output. |
10 | RESERVED | R/W | 0h | |
9-8 | FP | R/W | 0h | Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0h = The division factor is 3 1h = The division factor is 5 2h = The division factor is 8 |
7 | INV | R/W | 0h | Input Inversion This bit controls whether the selected input is inverted.
0h = Noninverted 1h = Inverted |
6-4 | RESERVED | R/W | 0h | |
3-0 | ISEL | R/W | 0h | Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved
0h = CCP of the corresponding capture compare unit 1h = Input pair CCPX of the capture compare unit. For CCP0 input pair is CCP1 and for CCP1 input pair is CCP0. 2h = CCP0 of the counter 3h = Trigger 4h = XOR of CCP inputs as input source (Used in Hall input mode). 5h = subscriber 0 event as input source. 6h = subscriber 1 event as input source. 7h = Comparator 0 output. 8h = Comparator 1 output. 9h = Comparator 2 output. |
PL is shown in Figure 25-95 and described in Table 25-82.
Return to the Summary Table.
This is the phase load register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PHASE | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15-0 | PHASE | R/W | 0h | Phase Load value
0h = Minimum value 00FFFFFFh = Maximum Value |
DBCTL is shown in Figure 25-96 and described in Table 25-83.
Return to the Summary Table.
The DBCTL register controls the dead band insertion of the pulse width modulated output.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FALLDELAY | ||||||
R/W- | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FALLDELAY | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | M1_ENABLE | RISEDELAY | |||||
R/W- | R/W- | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RISEDELAY | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R/W | 0h | |
27-16 | FALLDELAY | R/W | 0h | Fall Delay The number of TIMCLK periods inserted between the fall edge of CCP signal and the rise edge of CCP complimentary signal. 0h = Minimum value FFFh = Maximum Value |
15-13 | RESERVED | R/W | 0h | |
12 | M1_ENABLE | R/W | 0h | Dead Band Mode 1 Enable.
0h = Disabled 1h = Enabled |
11-0 | RISEDELAY | R/W | 0h | Rise Delay The number of TIMCLK periods inserted between the falling edge of CCP signal and the rising edge of CCP complimentary signal. 0h = Minimum value FFFh = Maximum Value |
TSEL is shown in Figure 25-97 and described in Table 25-84.
Return to the Summary Table.
The TSEL register controls the input trigger enable and selection of the trigger source. Trigger sources are generated by other peripherals through their respective publisher ports (subscribed in by the timer's subscriber port).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TE | RESERVED | ETSEL | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | 0h | |
9 | TE | R/W | 0h | Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field 0h = Triggers are not used. 1h = Triggers are used as selected by the IE, ITSEL and ETSEL fields. |
8-5 | RESERVED | R/W | 0h | |
4-0 | ETSEL | R/W | 0h | External Trigger Select. This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules. Refer to the SoC data sheet for details related to timer trigger sources. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use. 0h = TRIGx = External trigger input from TIM x. 1h = TRIGx = External trigger input from TIM x. 2h = TRIGx = External trigger input from TIM x. 3h = TRIGx = External trigger input from TIM x. 4h = TRIGx = External trigger input from TIM x. 5h = TRIGx = External trigger input from TIM x. 6h = TRIGx = External trigger input from TIM x. 7h = TRIGx = External trigger input from TIM x. 8h = TRIGx = External trigger input from TIM x. 9h = TRIGx = External trigger input from TIM x. Ah = TRIGx = External trigger input from TIM x. Bh = TRIGx = External trigger input from TIM x. Ch = TRIGx = External trigger input from TIM x. Dh = TRIGx = External trigger input from TIM x. Eh = TRIGx = External trigger input from TIM x. Fh = TRIGx = External trigger input from TIM x. 10h = TRIG_SUBx = External trigger input from subscriber port x. 11h = TRIG_SUBx = External trigger input from subscriber port x. |
RC is shown in Figure 25-98 and described in Table 25-85.
Return to the Summary Table.
Repeat counter is to reduce interrupt overhead. The repeat counter provides the mechanism to suppress un-necessary interrupts;
reducing the number of interrupts generated by each event type to 1 for the program number of
periods. Specifically, the repeat timer may suppress Load, Compare (up/down, normal/shadow),
and Zero events.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RC | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | RC | R | 0h | Repeat Counter Value
0h = Minimum value FFh = Maximum Value |
RCLD is shown in Figure 25-99 and described in Table 25-86.
Return to the Summary Table.
The load register value is transferred to the counter when the counter load input is asserted.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RCLD | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | |
7-0 | RCLD | R/W | 0h | Repeat Counter Load Value This field provides the value loaded into the repeat counter at a load event following the repeat counter value equaling 0. 0h = Minimum value FFh = Maximum Value |
QDIR is shown in Figure 25-100 and described in Table 25-87.
Return to the Summary Table.
The QDIR register provides the direction of count which is intended for use when operating the counter in QEI.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R- | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIR | ||||||||||||||
R- | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | |
0 | DIR | R | 0h | Direction of count
0h = Down (Phase B leads Phase A) 1h = Up (Phase A leads Phase B) |
FCTL is shown in Figure 25-101 and described in Table 25-88.
Return to the Summary Table.
The FCTL register controls the fault inputs, fault detection and error handling behavior.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FSENEXT2 | FSENEXT1 | FSENEXT0 | FSENAC2 | FSENAC1 | FSENAC0 | |
R/W- | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TFIM | RESERVED | FL | FI | RESERVED | FIEN | ||
R/W-0h | R/W- | R/W-0h | R/W-0h | R/W- | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | 0h | |
13 | FSENEXT2 | R/W | 0h | Specifies whether the external fault pin2 high/low is treated as fault condition.
0h = Fault Input is active low. 1h = Fault Input is active high. |
12 | FSENEXT1 | R/W | 0h | Specifies whether the external fault pin1 high/low is treated as fault condition.
0h = Fault Input is active low. 1h = Fault Input is active high. |
11 | FSENEXT0 | R/W | 0h | Specifies whether the external fault pin0 high/low is treated as fault condition.
0h = Fault Input is active low. 1h = Fault Input is active high. |
10 | FSENAC2 | R/W | 0h | Specifies whether the COMP2 output high/low is treated as fault condition.
0h = Fault Input is active low. 1h = Fault Input is active high. |
9 | FSENAC1 | R/W | 0h | Specifies whether the COMP1 output high/low is treated as fault condition.
0h = Fault Input is active low. 1h = Fault Input is active high. |
8 | FSENAC0 | R/W | 0h | Specifies whether the COMP0 output high/low is treated as fault condition.
0h = Fault Input is active low. 1h = Fault Input is active high. |
7 | TFIM | R/W | 0h | Trigger Fault Input Mask Specifies whether the selected trigger participates as a fault input. If enabled and the trigger asserts, the trigger is treated as a fault. 0h = Selected trigger does not participate in fault condition generation 1h = Selected trigger participates in fault condition generation |
6-5 | RESERVED | R/W | 0h | |
4-3 | FL | R/W | 0h | Fault Latch mode Specifies whether the fault condition is latched and configures the latch clear conditions. 0h = Overall fault condition is not dependent on the F bit in RIS 1h = Overall fault condition is dependent on the F bit in RIS 2h = Fault condition is latched. Fault condition is cleared on a zero event if the fault input is 0. 3h = Fault condition is latched. Fault condition is cleared on a load event if the fault input is 0. |
2 | FI | R/W | 0h | Fault Input Specifies whether the overall fault condition is dependent on the sensed fault pin. 0h = Overall Fault condition is not dependent on sensed input. 1h = Overall Fault condition is dependent on sensed input. |
1 | RESERVED | R/W | 0h | |
0 | FIEN | R/W | 0h | Fault Input Enable This bit enables the input for fault detection. 0h = Fault Input Disabled 1h = Fault Input Enabled |
FIFCTL is shown in Figure 25-102 and described in Table 25-89.
Return to the Summary Table.
The FIFCTL register controls the filtering for the fault input.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W- | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W- | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W- | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FILTEN | CPV | RESERVED | FP | |||
R/W- | R/W-0h | R/W-0h | R/W- | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | 0h | |
4 | FILTEN | R/W | 0h | Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to go directly to the optional pre-scale filter and then to the edge detect. 0h = Bypass 1h = Filtered. |
3 | CPV | R/W | 0h | Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting. 0h = Consecutive Periods. The input must be at a specific logic level for the period defined by FP before it is passed to the filter output. 1h = Voting. The filter ignores one clock of opposite logic over the filter period. I.e. Over FP samples of the input, up to 1 sample may be of an opposite logic value (glitch) without affecting the output |
2 | RESERVED | R/W | 0h | |
1-0 | FP | R/W | 0h | Filter Period This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering. 0h = Filter Period 3 1h = Filter Period 5 2h = Filter Period 8 |