SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 8-4 lists the memory-mapped registers for the IOMUX registers. All register offset addresses not listed in Table 8-4 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Group | Section |
---|---|---|---|---|
4h | PINCM | Pin Control Management Register in SECCFG region | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
PINCM is shown in Figure 8-4 and described in Table 8-6.
Return to the Summary Table.
Pin Control Management Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | WCOMP | WUEN | INV | HIZ1 | RESERVED | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DRV | HYSTEN | INENA | PIPU | PIPD | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WAKESTAT | RESERVED | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PC | RESERVED | PF | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | 0h | |
28 | WCOMP | R/W | 0h | Wakeup Compare Value bit
0h = Wakeup on a match of 0 1h = Wakeup on a match of 1 |
27 | WUEN | R/W | 0h | Wakeup Enable bit
0h = wakeup is disabled. 1h = wakeup is enabled |
26 | INV | R/W | 0h | Data inversion selection
0h = Data inversion is disabled. 1h = Data inversion is enabled |
25 | HIZ1 | R/W | 0h | High output value will tri-state the output when this bit is enabled
0h = open-drain is disabled. 1h = open-drain is enabled. |
24 | RESERVED | R/W | 0h | |
21 | RESERVED | R/W | 0h | |
20 | DRV | R/W | 0h | Drive strength control selection, for HS IOCELL only
0h = Drive setting of 0 selected 1h = Drive setting of 1 selected |
19 | HYSTEN | R/W | 0h | Hysteresis Enable Control Selection
0h = hysteresis is disabled. 1h = hysteresis is enabled |
18 | INENA | R/W | 0h | Input Enable Control Selection
0h = Input enable is disabled. 1h = Input enable is enabled. |
17 | PIPU | R/W | 0h | Pull Up control selection
0h = Pull up is disabled. 1h = Pull up is enabled |
16 | PIPD | R/W | 0h | Pull Down control selection
0h = Pull down is disabled. 1h = Pull down is enabled |
15-14 | RESERVED | R/W | 0h | |
13 | WAKESTAT | R | 0h | This has the IOPAD WAKEUP signal as status bit.
0h = wakeup source is NOT from this IOCELL 1h = wakeup source is from this IOCELL |
12-8 | RESERVED | R/W | 0h | |
7 | PC | R/W | 0h | Peripheral is “Connected”
0h = The output of the peripheral (and its output enable) will not propagate to the IOCELL 1h = The output latch of the dataflow will be “transparent” |
6 | RESERVED | R/W | 0h | |
5-0 | PF | R/W | 0h | Peripheral Function selection bits
0h = Reserved as unconnected 3Fh = An encoding per function that can be connected to this pin. |