SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

23.3 AES Registers

Table 23-12 lists the memory-mapped registers for the AES registers. All register offset addresses not listed in Table 23-12 should be considered as reserved locations and the register contents should not be modified.

Table 23-12 AES Registers
OffsetAcronymRegister NameGroupSection
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt Index RegisterCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1050hIIDXInterrupt Index RegisterDMA_TRIG0Go
1058hIMASKInterrupt maskDMA_TRIG0Go
1060hRISRaw interrupt statusDMA_TRIG0Go
1068hMISMasked interrupt statusDMA_TRIG0Go
1070hISETInterrupt setDMA_TRIG0Go
1078hICLRInterrupt clearDMA_TRIG0Go
1080hIIDXInterrupt Index RegisterDMA_TRIG1Go
1088hIMASKInterrupt maskDMA_TRIG1Go
1090hRISRaw interrupt statusDMA_TRIG1Go
1098hMISMasked interrupt statusDMA_TRIG1Go
10A0hISETInterrupt setDMA_TRIG1Go
10A8hICLRInterrupt clearDMA_TRIG1Go
10B0hIIDXInterrupt Index RegisterDMA_TRIG2Go
10B8hIMASKInterrupt maskDMA_TRIG2Go
10C0hRISRaw interrupt statusDMA_TRIG2Go
10C8hMISMasked interrupt statusDMA_TRIG2Go
10D0hISETInterrupt setDMA_TRIG2Go
10D8hICLRInterrupt clearDMA_TRIG2Go
10E0hEVT_MODEEvent ModeGo
1100hAESACTL0AES accelerator control register 0Go
1104hAESACTL1AES accelerator control register 1Go
1108hAESASTATaes accelerator status registerGo
110ChAESAKEYaes accelerator key registerGo
1110hAESADINaes accelerator data in registerGo
1114hAESADOUTaes accelerator data out registerGo
1118hAESAXDINaes accelerator xored data in registerGo
111ChAESAXINaes accelerator xored data in register (no trigger)Go

Complex bit access types are encoded to fit into small table cells. Table 23-13 shows the codes that are used for access types in this section.

Table 23-13 AES Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

23.3.1 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 23-10 and described in Table 23-14.

Return to the Summary Table.

Register to control the power state

Figure 23-10 PWREN
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDENABLE
R/W-0hR/WK-0h
Table 23-14 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR/W0h
0ENABLER/WK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

23.3.2 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 23-11 and described in Table 23-15.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 23-11 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
W-0hWK-0hWK-0h
Table 23-15 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDW0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

23.3.3 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 23-12 and described in Table 23-16.

Return to the Summary Table.

peripheral enable and reset status

Figure 23-12 STAT
3130292827262524
RESERVED
R-
2322212019181716
RESERVEDRESETSTKY
R-R-0h
15141312111098
RESERVED
R-
76543210
RESERVED
R-
Table 23-16 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

23.3.4 PDBGCTL (Offset = 1018h) [Reset = 00000003h]

PDBGCTL is shown in Figure 23-13 and described in Table 23-17.

Return to the Summary Table.

This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 23-13 PDBGCTL
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
RESERVEDSOFTFREE
R/W-R/W-1hR/W-1h
Table 23-17 PDBGCTL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1SOFTR/W1hSoft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0FREER/W1hFree run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

23.3.5 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 23-14 and described in Table 23-18.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-14 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 23-18 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = AES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT

23.3.6 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 23-15 and described in Table 23-19.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-15 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDAESRDY
R/W-0hR/W-0h
Table 23-19 IMASK Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0AESRDYR/W0hAES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask

23.3.7 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 23-16 and described in Table 23-20.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-16 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAESRDY
R-0hR-0h
Table 23-20 RIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0AESRDYR0hAES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT.
0h = Interrupt did not occur
1h = Interrupt occured

23.3.8 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 23-17 and described in Table 23-21.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-17 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAESRDY
R-0hR-0h
Table 23-21 MIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0AESRDYR0hAES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT.
0h = Interrupt did not occur
1h = Interrupt occured

23.3.9 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 23-18 and described in Table 23-22.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-18 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDAESRDY
W-0hW-0h
Table 23-22 ISET Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0AESRDYW0hAES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT.
0h = Writing 0 has no effect
1h = Set Interrupt

23.3.10 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 23-19 and described in Table 23-23.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-19 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDAESRDY
W-0hW-0h
Table 23-23 ICLR Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0h
0AESRDYW0hAES ready interrupt, set when the selected AES operation was completed and the result can be read from AESADOUT.
0h = Writing 0 has no effect
1h = Clear Interrupt

23.3.11 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 23-20 and described in Table 23-24.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-20 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 23-24 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
2h = AES trigger 0 DMA

23.3.12 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 23-21 and described in Table 23-25.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-21 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDDMA0RESERVED
R/W-0hR/W-0hR/W-0h
Table 23-25 IMASK Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1DMA0R/W0hDMA0 event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
0RESERVEDR/W0h

23.3.13 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 23-22 and described in Table 23-26.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-22 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA0RESERVED
R-0hR-0hR-0h
Table 23-26 RIS Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1DMA0R0hDMA0 event
0h = Interrupt did not occur
1h = Interrupt occured
0RESERVEDR0h

23.3.14 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 23-23 and described in Table 23-27.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-23 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA0RESERVED
R-0hR-0hR-0h
Table 23-27 MIS Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1DMA0R0hDMA0 event
0h = Interrupt did not occur
1h = Interrupt occured
0RESERVEDR0h

23.3.15 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 23-24 and described in Table 23-28.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-24 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDMA0RESERVED
W-0hW-0hW-0h
Table 23-28 ISET Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDW0h
1DMA0W0hDMA0
0h = Writing 0 has no effect
1h = Set Interrupt
0RESERVEDW0h

23.3.16 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 23-25 and described in Table 23-29.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-25 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDMA0RESERVED
W-0hW-0hW-0h
Table 23-29 ICLR Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDW0h
1DMA0W0hDMA0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
0RESERVEDW0h

23.3.17 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 23-26 and described in Table 23-30.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-26 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 23-30 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
3h = AES trigger 1 DMA

23.3.18 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 23-27 and described in Table 23-31.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-27 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDDMA1RESERVED
R/W-0hR/W-0hR/W-0h
Table 23-31 IMASK Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2DMA1R/W0hDMA1 event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
1-0RESERVEDR/W0h

23.3.19 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 23-28 and described in Table 23-32.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-28 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA1RESERVED
R-0hR-0hR-0h
Table 23-32 RIS Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2DMA1R0hDMA1 event
0h = Interrupt did not occur
1h = Interrupt occured
1-0RESERVEDR0h

23.3.20 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 23-29 and described in Table 23-33.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-29 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA1RESERVED
R-0hR-0hR-0h
Table 23-33 MIS Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2DMA1R0hDMA1 event
0h = Interrupt did not occur
1h = Interrupt occured
1-0RESERVEDR0h

23.3.21 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 23-30 and described in Table 23-34.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-30 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDMA1RESERVED
W-0hW-0hW-0h
Table 23-34 ISET Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDW0h
2DMA1W0hDMA1 event
0h = Writing 0 has no effect
1h = Set Interrupt
1-0RESERVEDW0h

23.3.22 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 23-31 and described in Table 23-35.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-31 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDMA1RESERVED
W-0hW-0hW-0h
Table 23-35 ICLR Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDW0h
2DMA1W0hDMA1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
1-0RESERVEDW0h

23.3.23 IIDX (Offset = 10B0h) [Reset = 00000000h]

IIDX is shown in Figure 23-32 and described in Table 23-36.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-32 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 23-36 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
4h = AES trigger 2 DMA

23.3.24 IMASK (Offset = 10B8h) [Reset = 00000000h]

IMASK is shown in Figure 23-33 and described in Table 23-37.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-33 IMASK
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDDMA2RESERVED
R/W-0hR/W-0hR/W-0h
Table 23-37 IMASK Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3DMA2R/W0hDMA2 event mask.
0h = Clear Interrupt Mask
1h = Set Interrrupt Mask
2-0RESERVEDR/W0h

23.3.25 RIS (Offset = 10C0h) [Reset = 00000000h]

RIS is shown in Figure 23-34 and described in Table 23-38.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-34 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA2RESERVED
R-0hR-0hR-0h
Table 23-38 RIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3DMA2R0hDMA2 event
0h = Interrupt did not occur
1h = Interrupt occured
2-0RESERVEDR0h

23.3.26 MIS (Offset = 10C8h) [Reset = 00000000h]

MIS is shown in Figure 23-35 and described in Table 23-39.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-35 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA2RESERVED
R-0hR-0hR-0h
Table 23-39 MIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3DMA2R0hDMA2 event
0h = Interrupt did not occur
1h = Interrupt occured
2-0RESERVEDR0h

23.3.27 ISET (Offset = 10D0h) [Reset = 00000000h]

ISET is shown in Figure 23-36 and described in Table 23-40.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-36 ISET
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDMA2RESERVED
W-0hW-0hW-0h
Table 23-40 ISET Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3DMA2W0hDMA2 event
0h = Writing 0 has no effect
1h = Set Interrupt
2-0RESERVEDW0h

23.3.28 ICLR (Offset = 10D8h) [Reset = 00000000h]

ICLR is shown in Figure 23-37 and described in Table 23-41.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-37 ICLR
3130292827262524
RESERVED
W-0h
2322212019181716
RESERVED
W-0h
15141312111098
RESERVED
W-0h
76543210
RESERVEDDMA2RESERVED
W-0hW-0hW-0h
Table 23-41 ICLR Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDW0h
3DMA2W0hDMA2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
2-0RESERVEDW0h

23.3.29 EVT_MODE (Offset = 10E0h) [Reset = 000000A9h]

EVT_MODE is shown in Figure 23-38 and described in Table 23-42.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 23-38 EVT_MODE
3130292827262524
RESERVED
R/W-
2322212019181716
RESERVED
R/W-
15141312111098
RESERVED
R/W-
76543210
EVT3_CFGEVT2_CFGEVT1_CFGINT0_CFG
R-2hR-2hR-2hR-1h
Table 23-42 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-6EVT3_CFGR2hEvent line mode select for event corresponding to none.DMA_TRIG2
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
5-4EVT2_CFGR2hEvent line mode select for event corresponding to none.DMA_TRIG1
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2EVT1_CFGR2hEvent line mode select for event corresponding to none.DMA_TRIG0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR1hEvent line mode select for event corresponding to none.CPU_INT
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

23.3.30 AESACTL0 (Offset = 1100h) [Reset = 00000000h]

AESACTL0 is shown in Figure 23-39 and described in Table 23-43.

Return to the Summary Table.

AES accelerator control register 0

Figure 23-39 AESACTL0
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
CMENRESERVEDERRFGRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
SWRSTCMxRESERVEDKLxOPx
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 23-43 AESACTL0 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15CMENR/W0hAESCMEN enables the support of the cipher modes ECB, CBC, OFB and CFB together with the DMA. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 0 = No DMA triggers are generated. 1 = DMA cipher mode support operation is enabled and the corresponding DMA triggers are generated.
0h = No DMA triggers are generated.
1h = DMA cipher mode support operation is enabled and the corresponding DMA triggers are generated.
14-12RESERVEDR/W0h
11ERRFGR/W0hAES error flag. AESAKEY or AESADIN were written while an AES operation was in progress. The bit must be cleared by software. 0b = No error 1b = Error occurred
0h (R/W) = No error
1h (R/W) = Error occurred
10-8RESERVEDR/W0h
7SWRSTR/W0hAES software reset. Immediately resets the complete AES accelerator module even when busy except for the AESRDYIE, the AESKLx and the AESOPx bits. It also clears the (internal) state memory. The AESSWRST bit is automatically reset and is always read as zero. 0b = No reset 1b = Reset AES accelerator module
0h = No reset.
1h = Reset AES accelerator module.
6-5CMxR/W0hAES cipher mode select. These bits are ignored for AESCMEN = 0. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00b = ECB 01b = CBC 10b = OFB 11b = CFB
0h = ECB
1h = CBC
2h = OFB
3h = CFB
4RESERVEDR/W0h
3-2KLxR/W0hAES key length.
These bits define which of the 1 AES standards is performed. The AESKLx bits are not reset by AESSWRST = 1. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.

0h = The key size is 128 bit.
2h = The key size is 256 bit.
1-0OPxR/W0hAES operation. The AESOPx bits are not reset by AESSWRST = 1. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00b = Encryption. 01b = Decryption. The provided key is the same key used for encryption. 10b = Generate first round key required for decryption. 11b = Decryption. The provided key is the first round key required for decryption.
0h (R/W) = Encryption
1h (R/W) = Decryption. The provided key is the same key used for encryption.
2h (R/W) = Generate first round key required for decryption.
3h (R/W) = Decryption. The provided key is the first round key required for decryption.

23.3.31 AESACTL1 (Offset = 1104h) [Reset = 00000000h]

AESACTL1 is shown in Figure 23-40 and described in Table 23-44.

Return to the Summary Table.

AES accelerator control register 1

Figure 23-40 AESACTL1
313029282726252423222120191817161514131211109876543210
RESERVEDBLKCNTx
R/W-0hR/W-0h
Table 23-44 AESACTL1 Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0BLKCNTxR/W0hCipher Block Counter. Number of blocks to be encrypted or decrypted with block cipher modes enabled (AESCMEN = 1). Ignored if AESCMEN = 0. The block counter decrements with each performed encryption or decryption. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0.
00h = Smallest value
FFh = Highest possible value

23.3.32 AESASTAT (Offset = 1108h) [Reset = 00000000h]

AESASTAT is shown in Figure 23-41 and described in Table 23-45.

Return to the Summary Table.

AES accelerator Status Register.

Figure 23-41 AESASTAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
DOUTCNTxDINCNTx
R-0hR-0h
76543210
KEYCNTxDOUTRDDINWRKEYWRBUSY
R-0hR-0hR/W-0hR/W-0hR-0h
Table 23-45 AESASTAT Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-12DOUTCNTxR0hBytes read from AESADOUT. Reset when AESDOUTRD is reset. If AESDOUTCNTx = 0 and AESDOUTRD = 0, no bytes were read. If AESDOUTCNTx = 0 and AESDOUTRD = 1, all bytes were read.
0h = Smallest possible value
Fh = Highest possible value
11-8DINCNTxR0hBytes written to AESADIN, AESAXDIN or AESAXIN. Reset when AESDINWR is reset. If AESDINCNTx = 0 and AESDINWR = 0, no bytes were written. If AESDINCNTx = 0 and AESDINWR = 1, all bytes were written.
0h = Smallest possible value
Fh = Highest possible value
7-4KEYCNTxR0hBytes written to AESAKEY when AESKLx = 00, half-words written to AESAKEY if AESKLx = b10. Reset when AESKEYWR is reset. If AESKEYCNTx = 0 and AESKEYWR = 0, no bytes were written. If AESKEYCNTx = 0 and AESKEYWR = 1, all bytes were written.
0h = Smallest possible value
Fh = Highest possible value
3DOUTRDR0hAll 16 bytes read from AESADOUT. AESDOUTRD is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, when the AES accelerator is busy, and when the output data is read again. 0 = Not all bytes read 1 = All bytes read
0h = Not all bytes read
1h = All bytes read
2DINWRR/W0hAll 16 bytes written to AESADIN, AESAXDIN or AESAXIN. Changing its state by software also resets the AESDINCNTx bits. AESDINWR is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, the start to (over)write the data, and when the AES accelerator is busy. Because it is reset when AESOPx or AESKLx is changed it can be set by software again to indicate that the current data is still valid. 0 = Not all bytes written 1 = All bytes written
0h = Not all bytes written
1h = All bytes written
1KEYWRR/W0hAll bytes written to AESAKEY. This bit can be modified by software but it must not be reset by software (1→0) if AESCMEN=1. Changing its state by software also resets the AESKEYCNTx bits. AESKEYWR is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, and the start to (over)write a new key. Because it is reset when AESOPx is changed it can be set by software again to indicate that the loaded key is still valid.

0h = Not all bytes written
1h = All bytes written
0BUSYR0hAES accelerator module busy; encryption, decryption, or key generation in progress. 0 = Not busy 1 = Busy
0h = Not busy
1h = Busy

23.3.33 AESAKEY (Offset = 110Ch) [Reset = 00000000h]

AESAKEY is shown in Figure 23-42 and described in Table 23-46.

Return to the Summary Table.

aes accelerator key register

Figure 23-42 AESAKEY
313029282726252423222120191817161514131211109876543210
KEY3xKEY2xKEY1xKEY0x
W-0hW-0hW-0hW-0h
Table 23-46 AESAKEY Field Descriptions
BitFieldTypeResetDescription
31-24KEY3xW0hAES key byte n+3 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1.
00h = Smallest possible value
FFh = Highest possible value
23-16KEY2xW0hAES key byte n+2 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1.
00h = Smallest possible value
FFh = Highest possible value
15-8KEY1xW0hAES key byte n+1 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1.
00h = Smallest possible value
FFh = Highest possible value
7-0KEY0xW0hAES key byte n when AESAKEY is written as word. AES next key byte when AESAKEY is written as byte. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1.
00h = Smallest possible value
FFh = Highest possible value

23.3.34 AESADIN (Offset = 1110h) [Reset = 00000000h]

AESADIN is shown in Figure 23-43 and described in Table 23-47.

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aes accelerator data in register

Figure 23-43 AESADIN
313029282726252423222120191817161514131211109876543210
DIN3xDIN2xDIN1xDIN0x
W-0hW-0hW-0hW-0h
Table 23-47 AESADIN Field Descriptions
BitFieldTypeResetDescription
31-24DIN3xW0hAES data in byte n+3 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
23-16DIN2xW0hAES data in byte n+2 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
15-8DIN1xW0hAES data in byte n+1 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
7-0DIN0xW0hAES data in byte n when AESADIN is written as word. AES next data in byte when AESADIN is written as byte. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value

23.3.35 AESADOUT (Offset = 1114h) [Reset = 00000000h]

AESADOUT is shown in Figure 23-44 and described in Table 23-48.

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aes accelerator data out register

Figure 23-44 AESADOUT
313029282726252423222120191817161514131211109876543210
DOUT3xDOUT2xDOUT1xDOUT0x
R-0hR-0hR-0hR-0h
Table 23-48 AESADOUT Field Descriptions
BitFieldTypeResetDescription
31-24DOUT3xR0hAES data out byte n+3 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access.
00h = Smallest possible value
FFh = Highest possible value
23-16DOUT2xR0hAES data out byte n+2 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access.
00h = Smallest possible value
FFh = Highest possible value
15-8DOUT1xR0hAES data out byte n+1 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access.
00h = Smallest possible value
FFh = Highest possible value
7-0DOUT0xR0hAES data out byte n when AESADOUT is read as word. AES next data out byte when AESADOUT is read as byte. Do not mix word and byte access.
00h = Smallest possible value
FFh = Highest possible value

23.3.36 AESAXDIN (Offset = 1118h) [Reset = 00000000h]

AESAXDIN is shown in Figure 23-45 and described in Table 23-49.

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aes accelerator xored data in register

Figure 23-45 AESAXDIN
313029282726252423222120191817161514131211109876543210
XDIN3xXDIN2xXDIN1xXDIN0x
W-0hW-0hW-0hW-0h
Table 23-49 AESAXDIN Field Descriptions
BitFieldTypeResetDescription
31-24XDIN3xW0hAES data in byte n+3 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
23-16XDIN2xW0hAES data in byte n+2 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
15-8XDIN1xW0hAES data in byte n+1 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
7-0XDIN0xW0hAES data in byte n when AESAXDIN is written as word. AES next data in byte when AESAXDIN is written as byte. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value

23.3.37 AESAXIN (Offset = 111Ch) [Reset = 00000000h]

AESAXIN is shown in Figure 23-46 and described in Table 23-50.

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aes accelerator xored data in register (no trigger)

Figure 23-46 AESAXIN
313029282726252423222120191817161514131211109876543210
XIN3xXIN2xXIN1xXIN0x
W-0hW-0hW-0hW-0h
Table 23-50 AESAXIN Field Descriptions
BitFieldTypeResetDescription
31-24XIN3xW0hAES data in byte n+3 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
23-16XIN2xW0hAES data in byte n+2 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
15-8XIN1xW0hAES data in byte n+1 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value
7-0XIN0xW0hAES data in byte n when AESAXIN is written as word. AES next data in byte when AESAXIN is written as byte. Do not mix word and byte access. Always reads as zero.
00h = Smallest possible value
FFh = Highest possible value