SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

17.3 SPI Registers

Table 17-7 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 17-7 should be considered as reserved locations and the register contents should not be modified.

Table 17-7 SPI Registers
Offset Acronym Register Name Group Section
4h SCLK SCLK Go
8h MOSI MOSI Go
Ch MISO MISO Go
18h CS0 SPI Chip Select 0 Go
1Ch CS1_MISO1 SPI Chip Select 1 Go
20h CS2_MISO2 SPI Chip Select 2 Go
24h CS3_CD_MISO3 SPI Chip Select 3 Go
204h SCLK FUPDATE version of SCLK Go
208h MOSI FUPDATE version of MOSI Go
20Ch MISO FUPDATE version of MISO Go
218h CS0 FUPDATE version of CS0 Go
21Ch CS1_MISO1 FUPDATE version of CS1 Go
220h CS2_MISO2 FUPDATE version of CS2 Go
224h CS3_CD_MISO3 FUPDATE version of CS3 Go
480h CPU_CONNECT_0 CPU Connect Go
504h DMA_MAP_RX DMA Map Go
505h DMA_TRIG_RX DMA Trigger Go
506h DMA_ENTRY_RX DMA Entry Go
508h DMA_MAP_TX DMA Map Go
509h DMA_TRIG_TX DMA Trigger Go
50Ah DMA_ENTRY_TX DMA Entry Go
800h PWREN Power enable Go
804h RSTCTL Reset Control Go
808h CLKCFG Peripheral Clock Configuration Register Go
814h STAT Status Register Go
1000h CLKDIV Clock Divider Go
1004h CLKSEL Clock Select for Ultra Low Power peripherals Go
1018h PDBGCTL Peripheral Debug Control Go
1020h IIDX Interrupt Index Register CPU_INT Go
1028h IMASK Interrupt mask CPU_INT Go
1030h RIS Raw interrupt status CPU_INT Go
1038h MIS Masked interrupt status CPU_INT Go
1040h ISET Interrupt set CPU_INT Go
1048h ICLR Interrupt clear CPU_INT Go
1050h IIDX Interrupt Index Register DMA_TRIG_RX Go
1058h IMASK Interrupt mask DMA_TRIG_RX Go
1060h RIS Raw interrupt status DMA_TRIG_RX Go
1068h MIS Masked interrupt status DMA_TRIG_RX Go
1070h ISET Interrupt set DMA_TRIG_RX Go
1078h ICLR Interrupt clear DMA_TRIG_RX Go
1080h IIDX Interrupt Index Register DMA_TRIG_TX Go
1088h IMASK Interrupt mask DMA_TRIG_TX Go
1090h RIS Raw interrupt status DMA_TRIG_TX Go
1098h MIS Masked interrupt status DMA_TRIG_TX Go
10A0h ISET Interrupt set DMA_TRIG_TX Go
10A8h ICLR Interrupt clear DMA_TRIG_TX Go
10E0h EVT_MODE Event Mode Go
10E4h INTCTL Interrupt control register Go
1100h CTL0 SPI control register 0 Go
1104h CTL1 SPI control register 1 Go
1108h CLKCTL Clock prescaler and divider register. Go
110Ch IFLS Interrupt FIFO Level Select Register Go
1110h STAT Status Register Go
1130h RXDATA RXDATA Register Go
1140h TXDATA TXDATA Register Go
1E00h TEST0 Test 0 Register Go

Complex bit access types are encoded to fit into small table cells. Table 17-8 shows the codes that are used for access types in this section.

Table 17-8 SPI Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R
-0		 Read
Returns 0s
Write Type
W W Write
WK W
K		 Write
Write protected by a key
Reset or Default Value
-n Value after reset or the default value

17.3.1 SCLK (Offset = 4h) [Reset = 00000000h]

SCLK is shown in Figure 17-9 and described in Table 17-9.

Return to the Summary Table.

SCLK Signal Controller : Clock Output Peripheral: Clock Input

Figure 17-9 SCLK
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-9 SCLK Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.2 MOSI (Offset = 8h) [Reset = 00000000h]

MOSI is shown in Figure 17-10 and described in Table 17-10.

Return to the Summary Table.

MOSI Signal Controller : Data Output Peripheral: Data Input

Figure 17-10 MOSI
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-10 MOSI Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.3 MISO (Offset = Ch) [Reset = 00000000h]

MISO is shown in Figure 17-11 and described in Table 17-11.

Return to the Summary Table.

MISO Signal Controller : Data Input Peripheral: Data Output

Figure 17-11 MISO
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-11 MISO Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.4 CS0 (Offset = 18h) [Reset = 00000000h]

CS0 is shown in Figure 17-12 and described in Table 17-12.

Return to the Summary Table.

SPI Chip Select 0: Controller : Output Peripheral: Input

Figure 17-12 CS0
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-12 CS0 Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.5 CS1_MISO1 (Offset = 1Ch) [Reset = 00000000h]

CS1_MISO1 is shown in Figure 17-13 and described in Table 17-13.

Return to the Summary Table.

SPI Chip Select 1 / MISO1 Controller : Output / Input Peripheral: - / Output

Figure 17-13 CS1_MISO1
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-13 CS1_MISO1 Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.6 CS2_MISO2 (Offset = 20h) [Reset = 00000000h]

CS2_MISO2 is shown in Figure 17-14 and described in Table 17-14.

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SPI Chip Select 2 / MISO2 Controller : Output / Input Peripheral: - / Output

Figure 17-14 CS2_MISO2
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-14 CS2_MISO2 Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.7 CS3_CD_MISO3 (Offset = 24h) [Reset = 00000000h]

CS3_CD_MISO3 is shown in Figure 17-15 and described in Table 17-15.

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SPI Chip Select 3 / Command Data / MISO3 Controller : Output / Output / Input Peripheral: - / - / Output

Figure 17-15 CS3_CD_MISO3
31 30 29 28 27 26 25 24
RESERVED GFLT SLEW WCOMP WUEN INV HIGHZ1 HIGHZ0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
RESERVED DRV HYSTEN INENA PIPU PIPD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
GSTATE RESERVED
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PSTATE RESERVED
R/W-0h R/W-0h
Table 17-15 CS3_CD_MISO3 Field Descriptions
Bit Field Type Reset Description
31 RESERVED R/W 0h
30 GFLT R/W 0h Glitch Filter Enable
0h = No internal glitch filter
1h = Use internal glitch filter
29 SLEW R/W 0h Reserved Slew Rate Control
0h = No Slew Rate Control
1h = Use Slew Rate Control
28 WCOMP R/W 0h Wake up compare value
0h = Match 0 will wake
1h = Match 1 will wake
27 WUEN R/W 0h Wake up enable
0h = Wake up not enabled
1h = Wake up enabled
26 INV R/W 0h Invert digital input/output relative to peripheral/GPIO
0h = Input and output are non-inverted
1h = Input and output are inverted
25 HIGHZ1 R/W 0h High-Z instead of high output
0h = Pin can be driven high
1h = Pin is tri-stated instead of driven high
24 HIGHZ0 R/W 0h High-Z instead of low output
0h = Pin can be driven low
1h = Pin is tri-stated instead of driven low
23 RESERVED R/W 0h
22-20 DRV R/W 0h Drive strength options
0h = Lowest drive strength
1h = Drive strength 2/8
2h = Drive strength 3/8
3h = Drive strength 4/8
4h = Drive strength 5/8
5h = Drive strength 6/8
6h = Drive strength 7/8
7h = Highest drive strength
19 HYSTEN R/W 0h Hysteresis enable
0h = No hysteresis
1h = Hysteresis on
18 INENA R/W 0h Input enable
0h = Inputs 0 to connected core
1h = Inputs IO pad value to connected core
17 PIPU R/W 0h Pull up enable
0h = No pull up
1h = Pull up
16 PIPD R/W 0h Pull down enable
0h = No pull down
1h = Pull down
15-14 GSTATE R/W 0h GPIO Channel State
0h = G-Channel is in Unassigned State
1h = G-Channel is in Handover State
2h = G-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = G-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
13-8 RESERVED R/W 0h
7-6 PSTATE R/W 0h Peripheral-Analog Channel State
0h = P-Channel is in Unassigned State
1h = P-Channel is in Handover State
2h = P-Channel is in Connected State and not Locked (That is F field is allowed to change without going back through Unassigned state)
3h = P-Channel is in Connected State and Locked (That is F field is not allowed to change to a different non-Zero value until both G and P channels go to Unassigned)
5-0 RESERVED R/W 0h

17.3.8 SCLK (Offset = 204h) [Reset = 00000000h]

SCLK is shown in Figure 17-16 and described in Table 17-16.

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FUPDATE version of SCLK

Figure 17-16 SCLK
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-16 SCLK Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.9 MOSI (Offset = 208h) [Reset = 00000000h]

MOSI is shown in Figure 17-17 and described in Table 17-17.

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FUPDATE version of MOSI

Figure 17-17 MOSI
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-17 MOSI Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.10 MISO (Offset = 20Ch) [Reset = 00000000h]

MISO is shown in Figure 17-18 and described in Table 17-18.

Return to the Summary Table.

FUPDATE version of MISO

Figure 17-18 MISO
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-18 MISO Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.11 CS0 (Offset = 218h) [Reset = 00000000h]

CS0 is shown in Figure 17-19 and described in Table 17-19.

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FUPDATE version of CS0

Figure 17-19 CS0
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-19 CS0 Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.12 CS1_MISO1 (Offset = 21Ch) [Reset = 00000000h]

CS1_MISO1 is shown in Figure 17-20 and described in Table 17-20.

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FUPDATE version of CS1_MISO1

Figure 17-20 CS1_MISO1
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-20 CS1_MISO1 Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.13 CS2_MISO2 (Offset = 220h) [Reset = 00000000h]

CS2_MISO2 is shown in Figure 17-21 and described in Table 17-21.

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FUPDATE version of CS2_MISO2

Figure 17-21 CS2_MISO2
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-21 CS2_MISO2 Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.14 CS3_CD_MISO3 (Offset = 224h) [Reset = 00000000h]

CS3_CD_MISO3 is shown in Figure 17-22 and described in Table 17-22.

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FUPDATE version of CS3_CD_MISO3

Figure 17-22 CS3_CD_MISO3
31 30 29 28 27 26 25 24
RESERVED IOADDR
W-0h W-0h
23 22 21 20 19 18 17 16
IOADDR
W-0h
15 14 13 12 11 10 9 8
IOADDR
W-0h
7 6 5 4 3 2 1 0
IOADDR LOCK GSEL
W-0h W-0h W-0h
Table 17-22 CS3_CD_MISO3 Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED W 0h
27-2 IOADDR W 0h IO Address. This is the address that corresponds to the SOC address[27:2] of the module IP instance specific IO signal in the “Full Write” subregion of the pinmux subregion.
1 LOCK W 0h Sets lock bit
0h = Writing this value has no effect
1h = Set channel lock bit
0 GSEL W 0h GPIO channel Select 0: Select the P-Channel for the F update 1: Select the G-Channel for the F update
0h = Select the P-Channel for the F update
1h = Select the G-Channel for the F update

17.3.15 CPU_CONNECT_0 (Offset = 480h) [Reset = 00000000h]

CPU_CONNECT_0 is shown in Figure 17-23 and described in Table 17-23.

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Directly connect peripheral publisher port to application processor

Figure 17-23 CPU_CONNECT_0
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED CPUSS0_CONN RESERVED
R/W-0h R/W-0h R/W-0h
Table 17-23 CPU_CONNECT_0 Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R/W 0h
1 CPUSS0_CONN R/W 0h CPUSS0 connect bit.
0h = The CPU is not connected.
1h = The CPU is connected.
0 RESERVED R/W 0h

17.3.16 DMA_MAP_RX (Offset = 504h) [Reset = 00h]

DMA_MAP_RX is shown in Figure 17-24 and described in Table 17-24.

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Trigger port ID in the DMA for this peripheral trigger

Figure 17-24 DMA_MAP_RX
7 6 5 4 3 2 1 0
RESERVED TRIG_ID
R-0h R-0h
Table 17-24 DMA_MAP_RX Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h
6-0 TRIG_ID R 0h The trigger port ID in the DMA for this peripheral trigger
0h = No trigger selected
1h = Trigger 1 selected
7Fh = Trigger 127 selected

17.3.17 DMA_TRIG_RX (Offset = 505h) [Reset = 00h]

DMA_TRIG_RX is shown in Figure 17-25 and described in Table 17-25.

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Trigger control and status register for this peripheral trigger

Figure 17-25 DMA_TRIG_RX
7 6 5 4 3 2 1 0
RESERVED THRHLD TRIGLOST STATECLR STATE
R/W-0h R-0h R-0h R-0/W-0h R-0h
Table 17-25 DMA_TRIG_RX Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0h
6-4 THRHLD R 0h The threshold for the DMA to accept the trigger request.
0h = Lowest threshold possible
6h = Highest threshold possible
3 TRIGLOST R 0h Sticky flag that is set whenever a trigger request is received while the trigger port is in TRIGGER_PEND or TRIGGERED. Cleared by writing to STATECLR.
0h = Trigger not lost
1h = Trigger was lost
2 STATECLR R-0/W 0h Clear trigger state. Writing 1 to this register clears any pending DMA trigger on this port and transitions the port to Untriggered state.
0h = Writing 0 has no effect
1h = Clear DMA trigger
1-0 STATE R 0h Returns the current state of the DMA tx trigger port
0h = Channel was not triggered
1h = Channel trigger is pending
2h = Channel was triggered

17.3.18 DMA_ENTRY_RX (Offset = 506h) [Reset = 0FFFh]

DMA_ENTRY_RX is shown in Figure 17-26 and described in Table 17-26.

Return to the Summary Table.

Descriptor connect to peripheral DMA trigger

Figure 17-26 DMA_ENTRY_RX
15 14 13 12 11 10 9 8
RESERVED ENTRY_ID
R/W- R/W-FFFh
7 6 5 4 3 2 1 0
ENTRY_ID
R/W-FFFh
Table 17-26 DMA_ENTRY_RX Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h
11-0 ENTRY_ID R/W FFFh The ID of the DMA descriptor that this trigger is routed to. This allows to ensure that another DMA channel could not listen or influence the DMA channel responsible for handling the data of this peripheral.
0h = DCLB index i=0-15. This can only be used with dedicated DCLBs.
Fh = DCLB index i=0-15. This can only be used with dedicated DCLBs.
10h = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system.
FFEh = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system.
FFFh = Trigger not enabled

17.3.19 DMA_MAP_TX (Offset = 508h) [Reset = 00h]

DMA_MAP_TX is shown in Figure 17-27 and described in Table 17-27.

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Trigger port ID in the DMA for this peripheral trigger

Figure 17-27 DMA_MAP_TX
7 6 5 4 3 2 1 0
RESERVED TRIG_ID
R-0h R-0h
Table 17-27 DMA_MAP_TX Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h
6-0 TRIG_ID R 0h The trigger port ID in the DMA for this peripheral trigger
0h = No trigger selected
1h = Trigger 1 selected
7Fh = Trigger 127 selected

17.3.20 DMA_TRIG_TX (Offset = 509h) [Reset = 00h]

DMA_TRIG_TX is shown in Figure 17-28 and described in Table 17-28.

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Trigger control and status register for this peripheral trigger

Figure 17-28 DMA_TRIG_TX
7 6 5 4 3 2 1 0
RESERVED THRHLD TRIGLOST STATECLR STATE
R/W-0h R-0h R-0h R-0/W-0h R-0h
Table 17-28 DMA_TRIG_TX Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0h
6-4 THRHLD R 0h The threshold for the DMA to accept the trigger request.
0h = Lowest threshold possible
6h = Highest threshold possible
3 TRIGLOST R 0h Sticky flag that is set whenever a trigger request is received while the trigger port is in TRIGGER_PEND or TRIGGERED. Cleared by writing to STATECLR.
0h = Trigger not lost
1h = Trigger was lost
2 STATECLR R-0/W 0h Clear trigger state. Writing 1 to this register clears any pending DMA trigger on this port and transitions the port to Untriggered state.
0h = Writing 0 has no effect
1h = Clear DMA trigger
1-0 STATE R 0h Returns the current state of the DMA tx trigger port
0h = Channel was not triggered
1h = Channel trigger is pending
2h = Channel was triggered

17.3.21 DMA_ENTRY_TX (Offset = 50Ah) [Reset = 0FFFh]

DMA_ENTRY_TX is shown in Figure 17-29 and described in Table 17-29.

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Descriptor connect to peripheral DMA trigger

Figure 17-29 DMA_ENTRY_TX
15 14 13 12 11 10 9 8
RESERVED ENTRY_ID
R/W- R/W-FFFh
7 6 5 4 3 2 1 0
ENTRY_ID
R/W-FFFh
Table 17-29 DMA_ENTRY_TX Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h
11-0 ENTRY_ID R/W FFFh The ID of the DMA descriptor that this trigger is routed to. This allows to ensure that another DMA channel could not listen or influence the DMA channel responsible for handling the data of this peripheral.
0h = DCLB index i=0-15. This can only be used with dedicated DCLBs.
Fh = DCLB index i=0-15. This can only be used with dedicated DCLBs.
10h = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system.
FFEh = DMA entry in RACE memory at index i=16-4094. This can only be used if limitless DMA is enabled in the system.
FFFh = Trigger not enabled

17.3.22 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 17-30 and described in Table 17-30.

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Register to control the power state

Figure 17-30 PWREN
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE
R/W-0h R/WK-0h
Table 17-30 PWREN Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to allow Power State Change
26h = KEY to allow write access to this register
23-1 RESERVED R/W 0h
0 ENABLE R/WK 0h Enable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

17.3.23 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 17-31 and described in Table 17-31.

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Register to control reset assertion and de-assertion

Figure 17-31 RSTCTL
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED RESETSTKYCLR RESETASSERT
W-0h WK-0h WK-0h
Table 17-31 RSTCTL Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h Unlock key
B1h = KEY to allow write access to this register
23-2 RESERVED W 0h
1 RESETSTKYCLR WK 0h Clear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0 RESETASSERT WK 0h Assert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

17.3.24 CLKCFG (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Figure 17-32 and described in Table 17-32.

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Peripheral Clock Configuration Register

Figure 17-32 CLKCFG
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED BLOCKASYNC
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Table 17-32 CLKCFG Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to Allow State Change -- 0xA9
A9h = key value to allow change field of GPRCM
23-9 RESERVED R/W 0h
8 BLOCKASYNC R/W 0h Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
0h = Not block async clock request
1h = Block async clock request
7-0 RESERVED R/W 0h

17.3.25 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 17-33 and described in Table 17-33.

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peripheral enable and reset status

Figure 17-33 STAT
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED RESETSTKY
R- R-0h
15 14 13 12 11 10 9 8
RESERVED
R-
7 6 5 4 3 2 1 0
RESERVED
R-
Table 17-33 STAT Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 RESETSTKY R 0h This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0 RESERVED R 0h

17.3.26 CLKDIV (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Figure 17-34 and described in Table 17-34.

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This register is used to specify module-specific divide ratio of the functional clock

Figure 17-34 CLKDIV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RATIO
R/W-0h R/W-0h
Table 17-34 CLKDIV Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R/W 0h
2-0 RATIO R/W 0h Selects divide ratio of module clock
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 3
3h = Divide clock source by 4
4h = Divide clock source by 5
5h = Divide clock source by 6
6h = Divide clock source by 7
7h = Divide clock source by 8

17.3.27 CLKSEL (Offset = 1004h) [Reset = 00000000h]

CLKSEL is shown in Figure 17-35 and described in Table 17-35.

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Clock source selection for peripherals

Figure 17-35 CLKSEL
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED SYSCLK_SEL MFCLK_SEL LFCLK_SEL RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 17-35 CLKSEL Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3 SYSCLK_SEL R/W 0h Selects SYSCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
2 MFCLK_SEL R/W 0h Selects MFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
1 LFCLK_SEL R/W 0h Selects LFCLK as clock source if enabled
0h = Does not select this clock as a source
1h = Select this clock as a source
0 RESERVED R/W 0h

17.3.28 PDBGCTL (Offset = 1018h) [Reset = 00000003h]

PDBGCTL is shown in Figure 17-36 and described in Table 17-36.

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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 17-36 PDBGCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED SOFT FREE
R/W- R/W-1h R/W-1h
Table 17-36 PDBGCTL Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R/W 0h
1 SOFT R/W 1h Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0 FREE R/W 1h Free run control
0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
1h = The peripheral ignores the state of the Core Halted input

17.3.29 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 17-37 and described in Table 17-37.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 17-37 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 17-37 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
00h = No interrupt pending
1h = RX FIFO Overflow Event/interrupt pending
2h = Transmit Parity Event/interrupt pending
3h = SPI receive time-out interrupt
4h = Receive Event/interrupt pending
5h = Transmit Event/interrupt pending
6h = Transmit Buffer Empty Event/interrupt pending
7h = End of Transmit Event/interrupt pending
8h = DMA Done for Receive Event/interrupt pending
9h = DMA Done for Transmit Event/interrupt pending
Ah = TX FIFO underflow interrupt
Bh = RX FIFO Full Interrupt

17.3.30 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 17-38 and described in Table 17-38.

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Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 17-38 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 17-38 IMASK Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R/W 0h
10 RXFULL R/W 0h RX FIFO Full Interrupt Mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9 TXFIFO_UNF R/W 0h TX FIFO underflow interrupt mask
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8 DMA_DONE_TX R/W 0h DMA Done 1 event for TX event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7 DMA_DONE_RX R/W 0h DMA Done 1 event for RX event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6 IDLE R/W 0h SPI Idle event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5 TXEMPTY R/W 0h Transmit FIFO Empty event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4 TX R/W 0h Transmit FIFO event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3 RX R/W 0h Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2 RTOUT R/W 0h Enable SPI Receive Time-Out event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1 PER R/W 0h Parity error event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0 RXFIFO_OVF R/W 0h RXFIFO overflow event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

17.3.31 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 17-39 and described in Table 17-39.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 17-39 RIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 17-39 RIS Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL R 0h RX FIFO Full Interrupt
0h = Interrupt did not occur
1h = Interrupt occurred
9 TXFIFO_UNF R 0h TX FIFO Underflow Interrupt
0h = Interrupt did not occur
1h = Interrupt occurred
8 DMA_DONE_TX R 0h DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0h = Interrupt did not occur
1h = Interrupt occurred
7 DMA_DONE_RX R 0h DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0h = Interrupt did not occur
1h = Interrupt occurred
6 IDLE R 0h SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low.
0h = Interrupt did not occur
1h = Interrupt occurred
5 TXEMPTY R 0h Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
0h = Interrupt did not occur
1h = Interrupt occurred
4 TX R 0h Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur
1h = Interrupt occurred
3 RX R 0h Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur
1h = Interrupt occurred
2 RTOUT R 0h SPI Receive Time-Out event.
0h = Interrupt did not occur
1h = Interrupt occurred
1 PER R 0h Parity error event: this bit is set if a Parity error has been detected
0h = Interrupt did not occur
1h = Interrupt occurred
0 RXFIFO_OVF R 0h RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur
1h = Interrupt occurred

17.3.32 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 17-40 and described in Table 17-40.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 17-40 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 17-40 MIS Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL R 0h RX FIFO Full Interrupt
0h = Interrupt did not occur
1h = Interrupt occurred
9 TXFIFO_UNF R 0h TX FIFO underflow interrupt
0h = Interrupt did not occur
1h = Interrupt occurred
8 DMA_DONE_TX R 0h Masked DMA Done 1 event for TX.
0h = Interrupt did not occur
1h = Interrupt occurred
7 DMA_DONE_RX R 0h Masked DMA Done 1 event for RX.
0h = Interrupt did not occur
1h = Interrupt occurred
6 IDLE R 0h Masked SPI IDLE mode event.
0h = Interrupt did not occur
1h = Interrupt occurred
5 TXEMPTY R 0h Masked Transmit FIFO Empty event.
0h = Interrupt did not occur
1h = Interrupt occurred
4 TX R 0h Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur
1h = Interrupt occurred
3 RX R 0h Masked receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur
1h = Interrupt occurred
2 RTOUT R 0h Masked SPI Receive Time-Out Interrupt.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1 PER R 0h Masked Parity error event: this bit if a Parity error has been detected
0h = Interrupt did not occur
1h = Interrupt occurred
0 RXFIFO_OVF R 0h Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur
1h = Interrupt occurred

17.3.33 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 17-41 and described in Table 17-41.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 17-41 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 17-41 ISET Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED W 0h
10 RXFULL W 0h Set RX FIFO Full Event
0h = Writing has no effect
1h = Set Interrupt
9 TXFIFO_UNF W 0h Set TX FIFO Underflow Event
0h = Writing has no effect
1h = Set interrupt
8 DMA_DONE_TX W 0h Set DMA Done 1 event for TX.
0h = Writing 0 has no effect
1h = Set Interrupt
7 DMA_DONE_RX W 0h Set DMA Done 1 event for RX.
0h = Writing 0 has no effect
1h = Set Interrupt
6 IDLE W 0h Set SPI IDLE mode event.
0h = Writing 0 has no effect
1h = Set Interrupt
5 TXEMPTY W 0h Set Transmit FIFO Empty event.
0h = Writing 0 has no effect
1h = Set Interrupt
4 TX W 0h Set Transmit FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
3 RX W 0h Set Receive FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
2 RTOUT W 0h Set SPI Receive Time-Out Event.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
1 PER W 0h Set Parity error event.
0h = Writing 0 has no effect
1h = Set Interrupt
0 RXFIFO_OVF W 0h Set RXFIFO overflow event.
0h = Writing 0 has no effect
1h = Set Interrupt

17.3.34 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 17-42 and described in Table 17-42.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 17-42 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 17-42 ICLR Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED W 0h
10 RXFULL W 0h Clear RX FIFO underflow event
0h = Writing has no effect
1h = Clear interrupt
9 TXFIFO_UNF W 0h Clear TXFIFO underflow event
0h = Writing has no effect
1h = Clear interrupt
8 DMA_DONE_TX W 0h Clear DMA Done 1 event for TX.
0h = Writing 0 has no effect
1h = Clear Interrupt
7 DMA_DONE_RX W 0h Clear DMA Done 1 event for RX.
0h = Writing 0 has no effect
1h = Clear Interrupt
6 IDLE W 0h Clear SPI IDLE mode event.
0h = Writing 0 has no effect
1h = Clear Interrupt
5 TXEMPTY W 0h Clear Transmit FIFO Empty event.
0h = Writing 0 has no effect
1h = Clear Interrupt
4 TX W 0h Clear Transmit FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
3 RX W 0h Clear Receive FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
2 RTOUT W 0h Clear SPI Receive Time-Out Event.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
1 PER W 0h Clear Parity error event.
0h = Writing 0 has no effect
1h = Clear Interrupt
0 RXFIFO_OVF W 0h Clear RXFIFO overflow event.
0h = Writing 0 has no effect
1h = Clear Interrupt

17.3.35 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 17-43 and described in Table 17-43.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 17-43 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 17-43 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
00h = No interrupt pending
3h = SPI receive time-out interrupt
4h = Receive Event/interrupt pending

17.3.36 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 17-44 and described in Table 17-44.

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Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 17-44 IMASK
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Table 17-44 IMASK Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3 RX R/W 0h Receive FIFO event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2 RTOUT R/W 0h SPI Receive Time-Out event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1-0 RESERVED R/W 0h

17.3.37 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 17-45 and described in Table 17-45.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 17-45 RIS
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8
RESERVED
R-
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R- R-0h R-0h R-
Table 17-45 RIS Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX R 0h Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur
1h = Interrupt occurred
2 RTOUT R 0h SPI Receive Time-Out Event.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1-0 RESERVED R 0h

17.3.38 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 17-46 and described in Table 17-46.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 17-46 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R-0h R-0h R-0h R-0h
Table 17-46 MIS Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX R 0h Receive FIFO event mask.
0h = Interrupt did not occur
1h = Interrupt occurred
2 RTOUT R 0h SPI Receive Time-Out event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1-0 RESERVED R 0h

17.3.39 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 17-47 and described in Table 17-47.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 17-47 ISET
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
W-0h W-0h W-0h W-0h
Table 17-47 ISET Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED W 0h
3 RX W 0h Set Receive FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
2 RTOUT W 0h Set SPI Receive Time-Out event.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
1-0 RESERVED W 0h

17.3.40 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 17-48 and described in Table 17-48.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 17-48 ICLR
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
W-0h W-0h W-0h W-0h
Table 17-48 ICLR Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED W 0h
3 RX W 0h Clear Receive FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
2 RTOUT W 0h Clear SPI Receive Time-Out event.
0h = Writing 0 has no effect
1h = Set Interrupt Mask
1-0 RESERVED W 0h

17.3.41 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 17-49 and described in Table 17-49.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 17-49 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 17-49 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
00h = No interrupt pending
5h = Transmit Event/interrupt pending

17.3.42 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 17-50 and described in Table 17-50.

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Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 17-50 IMASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R/W-0h R/W-0h R/W-0h
Table 17-50 IMASK Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R/W 0h
4 TX R/W 0h Transmit FIFO event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3-0 RESERVED R/W 0h

17.3.43 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 17-51 and described in Table 17-51.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 17-51 RIS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R- R-0h R-
Table 17-51 RIS Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX R 0h Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt.
0h = Interrupt did not occur
1h = Interrupt occurred
3-0 RESERVED R 0h

17.3.44 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 17-52 and described in Table 17-52.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 17-52 MIS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R-0h R-0h R-0h
Table 17-52 MIS Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX R 0h Masked Transmit FIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
3-0 RESERVED R 0h

17.3.45 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 17-53 and described in Table 17-53.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 17-53 ISET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
W-0h W-0h W-0h
Table 17-53 ISET Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED W 0h
4 TX W 0h Set Transmit FIFO event.
0h = Writing 0 has no effect
1h = Set Interrupt
3-0 RESERVED W 0h

17.3.46 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 17-54 and described in Table 17-54.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 17-54 ICLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
W-0h W-0h W-0h
Table 17-54 ICLR Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED W 0h
4 TX W 0h Clear Transmit FIFO event.
0h = Writing 0 has no effect
1h = Clear Interrupt
3-0 RESERVED W 0h

17.3.47 EVT_MODE (Offset = 10E0h) [Reset = 00000029h]

EVT_MODE is shown in Figure 17-55 and described in Table 17-55.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 17-55 EVT_MODE
31 30 29 28 27 26 25 24
RESERVED
R/W-
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED INT2_CFG INT1_CFG INT0_CFG
R/W- R-2h R-2h R-1h
Table 17-55 EVT_MODE Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R/W 0h
5-4 INT2_CFG R 2h Event line mode select for event corresponding to none.INT_EVENT2
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2 INT1_CFG R 2h Event line mode select for event corresponding to none.INT_EVENT1
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0 INT0_CFG R 1h Event line mode select for event corresponding to none.INT_EVENT0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

17.3.48 INTCTL (Offset = 10E4h) [Reset = 00000000h]

INTCTL is shown in Figure 17-56 and described in Table 17-56.

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Interrupt control register

Figure 17-56 INTCTL
31 30 29 28 27 26 25 24
RESERVED
R/W-
23 22 21 20 19 18 17 16
RESERVED
R/W-
15 14 13 12 11 10 9 8
RESERVED
R/W-
7 6 5 4 3 2 1 0
RESERVED INTEVAL
R/W- W-0h
Table 17-56 INTCTL Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R/W 0h
0 INTEVAL W 0h Writing a 1 to this field re-evaluates the interrupt sources.
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.

17.3.49 CTL0 (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Figure 17-57 and described in Table 17-57.

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SPI control register 0

Figure 17-57 CTL0
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8
RESERVED CSCLR CSSEL RESERVED SPH SPO
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PACKEN FRF DSS
R/W-0h R/W-0h R/W-0h
Table 17-57 CTL0 Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R/W 0h
14 CSCLR R/W 0h Clear shift register counter on CS inactive
This bit is relevant only in the peripheral, CTL1.CP=0.
0h = Disable automatic clear of shift register when CS goes to disable.
1h = Enable automatic clear of shift register when CS goes to disable.
13-12 CSSEL R/W 0h Select the CS line to control on data transfer
This bit is applicable for both controller/target mode
0h (R/W) = CS line select: 0
1h (R/W) = CS line select: 1
2h (R/W) = CS line select: 2
3h (R/W) = CS line select: 3
11-10 RESERVED R/W 0h
9 SPH R/W 0h CLKOUT phase (Motorola SPI frame format only)
This bit selects the clock edge that captures data and enables it to change state. It
has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
0h = Data is captured on the first clock edge transition.
1h = Data is captured on the second clock edge transition.
8 SPO R/W 0h CLKOUT polarity (Motorola SPI frame format only)
0h = SPI produces a steady state LOW value on the CLKOUT
1h = SPI produces a steady state HIGH value on the CLKOUT
7 PACKEN R/W 0h Packing Enable.
When 1, packing feature is enabled inside the IP
When 0, packing feature is disabled inside the IP

0h = Packing feature disabled
1h = Packing feature enabled
6-5 FRF R/W 0h Frame format Select
0h = Motorola SPI frame format (3 wire mode)
1h = Motorola SPI frame format (4 wire mode)
2h = TI synchronous serial frame format
3h = National Microwire frame format
4-0 DSS R/W 0h Data Size Select.
Values 0 - 2 are reserved and shall not be used.
3h = 4_BIT : 4-bit data
SPI allows only values up to 16 Bit
3h (R/W) = Data Size Select bits: 4
4h (R/W) = Data Size Select bits: 5
5h (R/W) = Data Size Select bits: 6
6h (R/W) = Data Size Select bits: 7
7h (R/W) = Data Size Select bits: 8
8h (R/W) = Data Size Select bits: 9
9h (R/W) = Data Size Select bits: 10
Ah (R/W) = Data Size Select bits: 11
Bh (R/W) = Data Size Select bits: 12
Ch (R/W) = Data Size Select bits: 13
Dh (R/W) = Data Size Select bits: 14
Eh (R/W) = Data Size Select bits: 15
Fh (R/W) = Data Size Select bits: 16

17.3.50 CTL1 (Offset = 1104h) [Reset = 00000004h]

CTL1 is shown in Figure 17-58 and described in Table 17-58.

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SPI control register 1

Figure 17-58 CTL1
31 30 29 28 27 26 25 24
RESERVED RXTIMEOUT
R/W-0h R/W-0h
23 22 21 20 19 18 17 16
REPEATTX
R/W-0h
15 14 13 12 11 10 9 8
CDMODE CDENABLE RESERVED PTEN
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED PES PREN MSB POD CP LBM ENABLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h
Table 17-58 CTL1 Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R/W 0h
29-24 RXTIMEOUT R/W 0h Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function.
0h = Smallest value
3Fh = Highest possible value
23-16 REPEATTX R/W 0h Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
0h = Smallest value
FFh = Highest possible value
15-12 CDMODE R/W 0h Command/Data Mode Value

When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information.

When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically

0: Manual mode with C/D signal as High
1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes.
15: Manual mode with C/D signal as Low.

0h = Manual mode: Data
0h = Smallest value
Fh = Manual mode: Command
11 CDENABLE R/W 0h Command/Data Mode enable
0h = CS3 is used for Chip Select
1h = CS3 is used as CD signal
10-9 RESERVED R/W 0h
8 PTEN R/W 0h Parity transmit enable
If enabled, parity transmission will be done for both controller and peripheral modes.
0h = Parity transmission is disabled
1h = Parity transmission is enabled
7 RESERVED R/W 0h
6 PES R/W 0h Even Parity Select
0h = Odd Parity mode
1h = Even Parity mode
5 PREN R/W 0h Parity receive enable
If enabled, parity reception check will be done for both controller and peripheral modes
In case of a parity miss-match the parity error flag RIS.PER will be set.
0h = Disable Parity receive function
1h = Enable Parity receive function
4 MSB R/W 0h MSB first select. Controls the direction of the receive and transmit shift register.
0h = LSB first
1h = MSB first
3 POD R/W 0h Peripheral-mode: Data output disabled
This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line.
POD can be used by the SPI peripheral to disable driving data on the line.
0h = SPI can drive the MISO output in peripheral mode.
1h = SPI cannot drive the MISO output in peripheral mode.
2 CP R/W 1h Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0.

0h = Select Peripheral mode
1h = Select Controller Mode
1 LBM R/W 0h Loop back mode
0h = Disable loopback mode
1h = Enable loopback mode
0 ENABLE R/W 0h SPI enable
0h = Disable module function
1h = Enable module function

17.3.51 CLKCTL (Offset = 1108h) [Reset = 00000000h]

CLKCTL is shown in Figure 17-59 and described in Table 17-59.

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Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.

Figure 17-59 CLKCTL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSAMPLE RESERVED
R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SCR
R/W-0h R/W-0h
Table 17-59 CLKCTL Field Descriptions
Bit Field Type Reset Description
31-28 DSAMPLE R/W 0h Delayed sampling value.
In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the data sheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system.
Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations.
0h = Smallest value
Fh = Highest possible value
27-10 RESERVED R/W 0h
9-0 SCR R/W 0h Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI functional clock frequency)/((SCR+1)×2). SCR is a value from 0-1023.
0h = Smallest value
3FFh = Highest possible value

17.3.52 IFLS (Offset = 110Ch) [Reset = 00000012h]

IFLS is shown in Figure 17-60 and described in Table 17-60.

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The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 17-60 IFLS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RXIFLSEL TXIFLSEL
R/W-0h R/W-2h R/W-2h
Table 17-60 IFLS Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R/W 0h
5-3 RXIFLSEL R/W 2h SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
0h = Reserved
1h = RX FIFO >= 1/4 full
2h = RX FIFO >= 1/2 full (default)
3h = RX FIFO >= 3/4 full
4h = Reserved
5h = RX FIFO is full
6h = Reserved
7h = Trigger when RX FIFO contains >= 1 frame
2-0 TXIFLSEL R/W 2h SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
0h = Reserved
1h = TX FIFO <= 3/4 empty
2h = TX FIFO <= 1/2 empty (default)
3h = TX FIFO <= 1/4 empty
4h = Reserved
5h = TX FIFO is empty
6h = Reserved
7h = Trigger when TX FIFO has >= 1 frame free.

17.3.53 STAT (Offset = 1110h) [Reset = 0000000Fh]

STAT is shown in Figure 17-61 and described in Table 17-61.

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Status Register

Figure 17-61 STAT
31 30 29 28 27 26 25 24
RESERVED
R-
23 22 21 20 19 18 17 16
RESERVED
R-
15 14 13 12 11 10 9 8
RESERVED
R-
7 6 5 4 3 2 1 0
RESERVED BUSY RNF RFE TNF TFE
R- R-0h R-1h R-1h R-1h R-1h
Table 17-61 STAT Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 BUSY R 0h Busy
0h = SPI is in idle mode.
1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
3 RNF R 1h Receive FIFO not full
0h = Receive FIFO is full.
1h = Receive FIFO is not full.
2 RFE R 1h Receive FIFO empty.
0h = Receive FIFO is not empty.
1h = Receive FIFO is empty.
1 TNF R 1h Transmit FIFO not full
0h = Transmit FIFO is full.
1h = Transmit FIFO is not full.
0 TFE R 1h Transmit FIFO empty.
0h = Transmit FIFO is not empty.
1h = Transmit FIFO is empty.

17.3.54 RXDATA (Offset = 1130h) [Reset = 00000000h]

RXDATA is shown in Figure 17-62 and described in Table 17-62.

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RXDATA Register
Reading this register returns value(s) of FIFO. If the FIFO is empty the last read value is returned.

Writing has not effect and is ignored.
When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value.

Figure 17-62 RXDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R-0h
Table 17-62 RXDATA Field Descriptions
Bit Field Type Reset Description
31-0 DATA R 0h Received Data
When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value.
As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer.
Received data less than 16 bits is automatically right justified in the receive buffer.
0h = Smallest value
FFFFFFFFh = Highest possible value

17.3.55 TXDATA (Offset = 1140h) [Reset = 00000000h]

TXDATA is shown in Figure 17-63 and described in Table 17-63.

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TXDATA Register
Writing puts the data into the TX FIFO. Reading this register returns the last written value.
When PACKEN=0, only the lower 16-bits of data written into the register is transferred to one 16-bits wide TX FIFO entry
When PACKEN=1, upper and lower 16-bits of 32-bit write data are transferred to two16-bits wide TX FIFO entry

Figure 17-63 TXDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
Table 17-63 TXDATA Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h Transmit Data

When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned.

When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate.

When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.

0h = Smallest value
FFFFFFFFh = Highest possible value

17.3.56 TEST0 (Offset = 1E00h) [Reset = 00000000h]

TEST0 is shown in Figure 17-64 and described in Table 17-64.

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Test 0 register.

Figure 17-64 TEST0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DTB_MUX_SEL
R/W-0h R/W-0h
Table 17-64 TEST0 Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W 0h
3-0 DTB_MUX_SEL R/W 0h This bit field is used to select DTB mux digital output signals.
0h = Disables DTB MUX
1h = Selects test group 1
2h = Selects test group 2
3h = Selects test group 3
4h = Selects test group 4
5h = Selects test group 5
6h = Selects test group 6
7h = Selects test group 7
8h = Selects test group 8
9h = Selects test group 9