SLAU846A June   2023  – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
    5. 1.5 NONMAIN Registers
    6. 1.6 Factory Constants
      1. 1.6.1 FACTORYREGION Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR) Supervisor
        2. 2.2.3.2 Brownout Reset (BOR) Supervisor
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Temperature Sensor
      6. 2.2.6 VBOOST for Analog Muxes
      7. 2.2.7 Peripheral Power Enable Control
        1. 2.2.7.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 SYSPLL Startup Monitor
          5. 2.3.4.3.5 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After POR
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Non-maskable Interrupt Event (NMI)
    5. 2.5 Quick Start Reference
      1. 2.5.1 Default Device Configuration
      2. 2.5.2 Leveraging MFCLK
      3. 2.5.3 Optimizing Power Consumption in STOP Mode
      4. 2.5.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.5.5 Increasing MCLK and ULPCLK Precision
      6. 2.5.6 Configuring MCLK for Maximum Speed
      7. 2.5.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.5.8 Optimizing for Lowest Wakeup Latency
      9. 2.5.9 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
    6. 2.6 SYSCTL Registers
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 DMA
    1. 4.1 DMA Overview
    2. 4.2 DMA Operation
      1. 4.2.1  Addressing Modes
      2. 4.2.2  Channel Types
      3. 4.2.3  Transfer Modes
        1. 4.2.3.1 Single Transfer
        2. 4.2.3.2 Block Transfer
        3. 4.2.3.3 Repeated Single Transfer
        4. 4.2.3.4 Repeated Block Transfer
        5. 4.2.3.5 Stride Mode
      4. 4.2.4  Extended Modes
        1. 4.2.4.1 Fill Mode
        2. 4.2.4.2 Table Mode
      5. 4.2.5  Initiating DMA Transfers
      6. 4.2.6  Stopping DMA Transfers
      7. 4.2.7  Channel Priorities
      8. 4.2.8  Burst Block Mode
      9. 4.2.9  Using DMA with System Interrupts
      10. 4.2.10 DMA Controller Interrupts
      11. 4.2.11 DMA Trigger Event Status
      12. 4.2.12 DMA Operating Mode Support
        1. 4.2.12.1 Transfer in RUN Mode
        2. 4.2.12.2 Transfer in SLEEP Mode
        3. 4.2.12.3 Transfer in STOP Mode
        4. 4.2.12.4 Transfers in STANDBY Mode
      13. 4.2.13 DMA Address and Data Errors
      14. 4.2.14 Interrupt and Event Support
    3. 4.3 DMA Registers
  7. 5 MATHACL
    1. 5.1 Overview
    2. 5.2 Data Format
      1. 5.2.1 Unsigned 32-bit integers
      2. 5.2.2 Signed 32-bit integers
      3. 5.2.3 Unsigned 32-bit numbers
      4. 5.2.4 Signed 32-bit numbers
    3. 5.3 Basic Operation
    4. 5.4 Configuration Details with Examples
      1. 5.4.1 Sine and Cosine (SINCOS)
      2. 5.4.2 Arc Tangent (ATAN2)
      3. 5.4.3 Square Root (SQRT)
      4. 5.4.4 Division (DIV)
      5. 5.4.5 Multiplication
        1. 5.4.5.1 Multiply32 (MPY32)
        2. 5.4.5.2 Square32 (SQUARE32)
        3. 5.4.5.3 Multiply64 (MPY64)
        4. 5.4.5.4 Square64 (SQUARE64)
      6. 5.4.6 Multiply-Accumulate (MAC)
      7. 5.4.7 Square Accumulate (SAC)
    5. 5.5 MATHACL Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
      2. 6.5.2 ECC Error Handling
        1. 6.5.2.1 Single bit (correctable) errors
        2. 6.5.2.2 Dual bit (uncorrectable) errors
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX (PINCMx) Register Format
    4. 8.4 IOMUX Registers
  11. 9 GPIO
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Simultaneous Sampling
        2. 10.2.12.2 Window Comparator
        3. 10.2.12.3 DMA and FIFO Operation
        4. 10.2.12.4 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11COMP
    1. 11.1 Comparator Overview
    2. 11.2 Comparator Operation
      1. 11.2.1  Comparator Configuration
      2. 11.2.2  Comparator Channels Selection
      3. 11.2.3  Comparator Output
      4. 11.2.4  Output Filter
      5. 11.2.5  Sampled Output Mode
      6. 11.2.6  Blanking Mode
      7. 11.2.7  Reference Voltage Generator
      8. 11.2.8  Window Comparator Mode
      9. 11.2.9  Comparator Hysteresis
      10. 11.2.10 Input SHORT Switch
      11. 11.2.11 Interrupt and Events Support
        1. 11.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 11.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 11.2.11.3 Generic Event Subscribers
    3. 11.3 COMP Registers
  14. 12OPA
    1. 12.1 OPA Overview
    2. 12.2 OPA Operation
      1. 12.2.1 Analog Core
      2. 12.2.2 Power Up Behavior
      3. 12.2.3 Inputs
      4. 12.2.4 Output
      5. 12.2.5 Clock Requirements
      6. 12.2.6 Chopping
      7. 12.2.7 OPA Amplifier Modes
        1. 12.2.7.1 General-Purpose Mode
        2. 12.2.7.2 Buffer Mode
        3. 12.2.7.3 OPA PGA Mode
          1. 12.2.7.3.1 Inverting PGA Mode
          2. 12.2.7.3.2 Non-inverting PGA Mode
        4. 12.2.7.4 Difference Amplifier Mode
        5. 12.2.7.5 Cascade Amplifier Mode
      8. 12.2.8 OPA Configuration Selection
      9. 12.2.9 Burnout Current Source
    3. 12.3 OA Registers
  15. 13GPAMP
    1. 13.1 GPAMP Overview
    2. 13.2 GPAMP Operation
      1. 13.2.1 Analog Core
      2. 13.2.2 Power Up Behavior
      3. 13.2.3 Inputs
      4. 13.2.4 Output
      5. 13.2.5 GPAMP Amplifier Modes
        1. 13.2.5.1 General-Purpose Mode
        2. 13.2.5.2 ADC Buffer Mode
        3. 13.2.5.3 Unity Gain Mode
      6. 13.2.6 Chopping
    3. 13.3 GPAMP Registers
  16. 14DAC
    1. 14.1 DAC Introduction
    2. 14.2 DAC Operation
      1. 14.2.1  DAC Core
      2. 14.2.2  DAC Output
      3. 14.2.3  DAC Voltage Reference
      4. 14.2.4  DAC Output Buffers
      5. 14.2.5  DAC Data Formats
      6. 14.2.6  Sample Time Generator
      7. 14.2.7  DAC FIFO Structure
        1. 14.2.7.1 Loading Data From FIFO to Internal DAC Data Register
      8. 14.2.8  DAC Operation With DMA Controller
        1. 14.2.8.1 DMA Trigger Interface
        2. 14.2.8.2 DMA Status Interface
        3. 14.2.8.3 DMA Trigger Generation Scheme
      9. 14.2.9  DAC Operation With CPU
        1. 14.2.9.1 Interrupt conditions for DAC operation with CPU
      10. 14.2.10 Data Register Format
      11. 14.2.11 DAC Output Amplifier Offset Calibration
      12. 14.2.12 Interrupt and Event Support
        1. 14.2.12.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.12.2 Generic Event Publisher (GEN_EVENT)
        3. 14.2.12.3 DMA Trigger Event Publisher
        4. 14.2.12.4 Generic Event Subscriber (FSUB_0)
    3. 14.3 DAC12 Registers
  17. 15VREF
    1. 15.1 VREF Overview
    2. 15.2 VREF Operation
      1. 15.2.1 Internal Reference Generation
      2. 15.2.2 External Reference Input
      3. 15.2.3 Analog Peripheral Interface
    3. 15.3 VREF Registers
  18. 16UART
    1. 16.1 UART Overview
      1. 16.1.1 Purpose of the Peripheral
      2. 16.1.2 Features
      3. 16.1.3 Functional Block Diagram
    2. 16.2 UART Operation
      1. 16.2.1 Clock Control
      2. 16.2.2 Signal Descriptions
      3. 16.2.3 General Architecture and Protocol
        1. 16.2.3.1  Transmit Receive Logic
        2. 16.2.3.2  Bit Sampling
        3. 16.2.3.3  Majority Voting Feature
        4. 16.2.3.4  Baud Rate Generation
        5. 16.2.3.5  Data Transmission
        6. 16.2.3.6  Error and Status
        7. 16.2.3.7  Local Interconnect Network (LIN) Support
          1. 16.2.3.7.1 LIN Responder Transmission Delay
        8. 16.2.3.8  Flow Control
        9. 16.2.3.9  Idle-Line Multiprocessor
        10. 16.2.3.10 9-Bit UART Mode
        11. 16.2.3.11 RS485 Support
        12. 16.2.3.12 DALI Protocol
        13. 16.2.3.13 Manchester Encoding and Decoding
        14. 16.2.3.14 IrDA Encoding and Decoding
        15. 16.2.3.15 ISO7816 Smart Card Support
        16. 16.2.3.16 Address Detection
        17. 16.2.3.17 FIFO Operation
        18. 16.2.3.18 Loopback Operation
        19. 16.2.3.19 Glitch Suppression
      4. 16.2.4 Low Power Operation
      5. 16.2.5 Reset Considerations
      6. 16.2.6 Initialization
      7. 16.2.7 Interrupt and Events Support
        1. 16.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 16.2.8 Emulation Modes
    3. 16.3 UART Registers
  19. 17SPI
    1. 17.1 SPI Overview
      1. 17.1.1 Purpose of the Peripheral
      2. 17.1.2 Features
      3. 17.1.3 Functional Block Diagram
      4. 17.1.4 External Connections and Signal Descriptions
    2. 17.2 SPI Operation
      1. 17.2.1 Clock Control
      2. 17.2.2 General Architecture
        1. 17.2.2.1 Chip Select and Command Handling
          1. 17.2.2.1.1 Chip Select Control
          2. 17.2.2.1.2 Command Data Control
        2. 17.2.2.2 Data Format
        3. 17.2.2.3 Delayed data sampling
        4. 17.2.2.4 Clock Generation
        5. 17.2.2.5 FIFO Operation
        6. 17.2.2.6 Loopback mode
        7. 17.2.2.7 DMA Operation
        8. 17.2.2.8 Repeat Transfer mode
        9. 17.2.2.9 Low Power Mode
      3. 17.2.3 Protocol Descriptions
        1. 17.2.3.1 Motorola SPI Frame Format
        2. 17.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 17.2.4 Reset Considerations
      5. 17.2.5 Initialization
      6. 17.2.6 Interrupt and Events Support
        1. 17.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 17.2.7 Emulation Modes
    3. 17.3 SPI Registers
  20. 18I2C
    1. 18.1 I2C Overview
      1. 18.1.1 Purpose of the Peripheral
      2. 18.1.2 Features
      3. 18.1.3 Functional Block Diagram
      4. 18.1.4 Environment and External Connections
    2. 18.2 I2C Operation
      1. 18.2.1 Clock Control
        1. 18.2.1.1 Clock Select and I2C Speed
        2. 18.2.1.2 Clock Startup
      2. 18.2.2 Signal Descriptions
      3. 18.2.3 General Architecture
        1. 18.2.3.1  I2C Bus Functional Overview
        2. 18.2.3.2  START and STOP Conditions
        3. 18.2.3.3  Data Format with 7-Bit Address
        4. 18.2.3.4  Acknowledge
        5. 18.2.3.5  Repeated Start
        6. 18.2.3.6  SCL Clock Low Timeout
        7. 18.2.3.7  Clock Stretching
        8. 18.2.3.8  Dual Address
        9. 18.2.3.9  Arbitration
        10. 18.2.3.10 Multiple Controller Mode
        11. 18.2.3.11 Glitch Suppression
        12. 18.2.3.12 FIFO operation
          1. 18.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 18.2.3.13 Loopback mode
        14. 18.2.3.14 Burst Mode
        15. 18.2.3.15 DMA Operation
        16. 18.2.3.16 Low-Power Operation
      4. 18.2.4 Protocol Descriptions
        1. 18.2.4.1 I2C Controller Mode
          1. 18.2.4.1.1 Controller Configuration
          2. 18.2.4.1.2 Controller Mode Operation
          3. 18.2.4.1.3 Read On TX Empty
        2. 18.2.4.2 I2C Target Mode
          1. 18.2.4.2.1 Target Mode Operation
      5. 18.2.5 Reset Considerations
      6. 18.2.6 Initialization
      7. 18.2.7 Interrupt and Events Support
        1. 18.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 18.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 18.2.8 Emulation Modes
  21. 19I2C Registers
  22. 20CAN-FD
    1. 20.1 MCAN Overview
      1. 20.1.1 MCAN Features
    2. 20.2 MCAN Environment
    3. 20.3 CAN Network Basics
    4. 20.4 MCAN Functional Description
      1. 20.4.1  Clock Set up
      2. 20.4.2  Module Clocking Requirements
      3. 20.4.3  Interrupt Requests
      4. 20.4.4  Operating Modes
        1. 20.4.4.1 Normal Operation
        2. 20.4.4.2 CAN Classic
        3. 20.4.4.3 CAN FD Operation
      5. 20.4.5  Software Initialization
      6. 20.4.6  Transmitter Delay Compensation
        1. 20.4.6.1 Description
        2. 20.4.6.2 Transmitter Delay Compensation Measurement
      7. 20.4.7  Restricted Operation Mode
      8. 20.4.8  Bus Monitoring Mode
      9. 20.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 20.4.9.1 Frame Transmission in DAR Mode
      10. 20.4.10 Clock Stop Mode
        1. 20.4.10.1 Suspend Mode
        2. 20.4.10.2 Wakeup Request
      11. 20.4.11 Test Modes
        1. 20.4.11.1 External Loop Back Mode
        2. 20.4.11.2 Internal Loop Back Mode
      12. 20.4.12 Timestamp Generation
        1. 20.4.12.1 External Timestamp Counter
      13. 20.4.13 Timeout Counter
      14. 20.4.14 Safety
        1. 20.4.14.1 ECC Wrapper
        2. 20.4.14.2 ECC Aggregator
          1. 20.4.14.2.1 ECC Aggregator Overview
          2. 20.4.14.2.2 ECC Aggregator Registers
        3. 20.4.14.3 Reads to ECC Control and Status Registers
        4. 20.4.14.4 ECC Interrupts
      15. 20.4.15 Tx Handling
        1. 20.4.15.1 Transmit Pause
        2. 20.4.15.2 Dedicated Tx Buffers
        3. 20.4.15.3 Tx FIFO
        4. 20.4.15.4 Tx Queue
        5. 20.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 20.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 20.4.15.7 Transmit Cancellation
        8. 20.4.15.8 Tx Event Handling
        9. 20.4.15.9 FIFO Acknowledge Handling
      16. 20.4.16 Rx Handling
        1. 20.4.16.1 Acceptance Filtering
          1. 20.4.16.1.1 Range Filter
          2. 20.4.16.1.2 Filter for Specific IDs
          3. 20.4.16.1.3 Classic Bit Mask Filter
          4. 20.4.16.1.4 Standard Message ID Filtering
          5. 20.4.16.1.5 Extended Message ID Filtering
      17. 20.4.17 Rx FIFOs
        1. 20.4.17.1 Rx FIFO Blocking Mode
        2. 20.4.17.2 Rx FIFO Overwrite Mode
      18. 20.4.18 Dedicated Rx Buffers
        1. 20.4.18.1 Rx Buffer Handling
      19. 20.4.19 Message RAM
        1. 20.4.19.1 Message RAM Configuration
        2. 20.4.19.2 Rx Buffer and FIFO Element
        3. 20.4.19.3 Tx Buffer Element
        4. 20.4.19.4 Tx Event FIFO Element
        5. 20.4.19.5 Standard Message ID Filter Element
        6. 20.4.19.6 Extended Message ID Filter Element
    5. 20.5 MCAN Integration
    6. 20.6 Interrupt and Event Support
      1. 20.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 20.7 MCAN Registers
  23. 21MCAN Registers
  24. 22CRC
    1. 22.1 CRC Overview
      1. 22.1.1 CRC16-CCITT
      2. 22.1.2 CRC32-ISO3309
    2. 22.2 CRC Operation
      1. 22.2.1 CRC Generator Implementation
      2. 22.2.2 Configuration
        1. 22.2.2.1 Polynomial Selection
        2. 22.2.2.2 Bit Order
        3. 22.2.2.3 Byte Swap
        4. 22.2.2.4 Byte Order
        5. 22.2.2.5 CRC C Library Compatibility
    3. 22.3 CRC Registers
  25. 23AES
    1. 23.1 AES Overview
      1. 23.1.1 AES Performance
    2. 23.2 AES Operation
      1. 23.2.1 AES Register Access Rules
      2. 23.2.2 Loading the Key
      3. 23.2.3 Loading Data
      4. 23.2.4 Reading Data
      5. 23.2.5 Triggering an Encryption or Decryption
      6. 23.2.6 Single Block Operations
        1. 23.2.6.1 Encryption
        2. 23.2.6.2 Decryption
          1. 23.2.6.2.1 Pregenerating a Decryption Key
      7. 23.2.7 Block Cipher Mode Operations
        1. 23.2.7.1 Electronic Codebook (ECB) Mode
          1. 23.2.7.1.1 ECB Encryption
          2. 23.2.7.1.2 ECB Decryption
        2. 23.2.7.2 Cipher Block Chaining (CBC) Mode
          1. 23.2.7.2.1 CBC Encryption
          2. 23.2.7.2.2 CBC Decryption
        3. 23.2.7.3 Output Feedback (OFB) Mode
          1. 23.2.7.3.1 OFB Encryption
          2. 23.2.7.3.2 OFB Decryption
        4. 23.2.7.4 Cipher Feedback (CFB) Mode
          1. 23.2.7.4.1 CFB Encryption
          2. 23.2.7.4.2 CFB Decryption
        5. 23.2.7.5 Counter (CTR) Mode
          1. 23.2.7.5.1 CTR Encryption
          2. 23.2.7.5.2 CTR Decryption
      8. 23.2.8 AES Events
        1. 23.2.8.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 23.2.8.2 DMA Trigger Event Publisher (DMA_TRIG0)
        3. 23.2.8.3 DMA Trigger Event Publisher (DMA_TRIG1)
        4. 23.2.8.4 DMA Trigger Event Publisher (DMA_TRIG2)
    3. 23.3 AES Registers
  26. 24TRNG
    1. 24.1 TRNG Overview
    2. 24.2 TRNG Operation
      1. 24.2.1 TRNG Generation Data Path
      2. 24.2.2 Clock Configuration and Output Rate
      3. 24.2.3 Behavior in Low Power Modes
      4. 24.2.4 Health Tests
        1. 24.2.4.1 Digital Block Startup Self-Test
        2. 24.2.4.2 Analog Block Startup Self-Test
        3. 24.2.4.3 Runtime Health Test
          1. 24.2.4.3.1 Repetition Count Test
          2. 24.2.4.3.2 Adaptive Proportion Test
          3. 24.2.4.3.3 Handling Runtime Health Test Failures
      5. 24.2.5 Configuration
        1. 24.2.5.1 TRNG State Machine
          1. 24.2.5.1.1 Changing TRNG States
        2. 24.2.5.2 Using the TRNG
        3. 24.2.5.3 TRNG Events
          1. 24.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 24.3 TRNG Registers
  27. 25Timers (TIMx)
    1. 25.1 TIMx Overview
      1. 25.1.1 TIMG Overview
        1. 25.1.1.1 TIMG Features
        2. 25.1.1.2 Functional Block Diagram
      2. 25.1.2 TIMA Overview
        1. 25.1.2.1 TIMA Features
        2. 25.1.2.2 Functional Block Diagram
      3. 25.1.3 TIMx Instance Configuration
    2. 25.2 TIMx Operation
      1. 25.2.1  Timer Counter
        1. 25.2.1.1 Clock Source Select and Prescaler
          1. 25.2.1.1.1 Internal Clock and Prescaler
          2. 25.2.1.1.2 External Signal Trigger
        2. 25.2.1.2 Repeat Counter (TIMA only)
      2. 25.2.2  Counting Mode Control
        1. 25.2.2.1 One-shot and Periodic Modes
        2. 25.2.2.2 Down Counting Mode
        3. 25.2.2.3 Up/Down Counting Mode
        4. 25.2.2.4 Up Counting Mode
        5. 25.2.2.5 Phase Load (TIMA only)
      3. 25.2.3  Capture/Compare Module
        1. 25.2.3.1 Capture Mode
          1. 25.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 25.2.3.1.1.1 CCP Input Edge Synchronization
            2. 25.2.3.1.1.2 CCP Input Pulse Conditions
            3. 25.2.3.1.1.3 Counter Control Operation
            4. 25.2.3.1.1.4 CCP Input Filtering
            5. 25.2.3.1.1.5 Input Selection
          2. 25.2.3.1.2 Use Cases
            1. 25.2.3.1.2.1 Edge Time Capture
            2. 25.2.3.1.2.2 Period Capture
            3. 25.2.3.1.2.3 Pulse Width Capture
            4. 25.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 25.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 25.2.3.1.3.1 QEI With 2-Signal
            2. 25.2.3.1.3.2 QEI With Index Input
            3. 25.2.3.1.3.3 QEI Error Detection
          4. 25.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 25.2.3.2 Compare Mode
          1. 25.2.3.2.1 Edge Count
      4. 25.2.4  Shadow Load and Shadow Compare
        1. 25.2.4.1 Shadow Load
        2. 25.2.4.2 Shadow Compare
      5. 25.2.5  Output Generator
        1. 25.2.5.1 Configuration
        2. 25.2.5.2 Use Cases
          1. 25.2.5.2.1 Edge-Aligned PWM
          2. 25.2.5.2.2 Center-Aligned PWM
          3. 25.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 25.2.5.2.4 Complementary PWM with Deadband Insertion (TIMA only)
        3. 25.2.5.3 Forced Output
      6. 25.2.6  Fault Handler (TIMA only)
        1. 25.2.6.1 Fault Input Conditioning
        2. 25.2.6.2 Fault Input Sources
        3. 25.2.6.3 Counter Behavior With Fault Conditions
        4. 25.2.6.4 Output Behavior With Fault Conditions
      7. 25.2.7  Synchronization With Cross Trigger
        1. 25.2.7.1 Main Timer Cross Trigger Configuration
        2. 25.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 25.2.8  Low Power Operation
      9. 25.2.9  Interrupt and Event Support
        1. 25.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 25.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 25.2.10 Debug Handler (TIMA only)
    3. 25.3 Timers (TIMx) Registers
  28. 26RTC
    1. 26.1 Overview
    2. 26.2 Basic Operation
    3. 26.3 Configuration
      1. 26.3.1 Clocking
      2. 26.3.2 Reading and Writing to RTC Peripheral Registers
      3. 26.3.3 Binary vs. BCD
      4. 26.3.4 Leap Year Handling
      5. 26.3.5 Calendar Alarm Configuration
      6. 26.3.6 Interval Alarm Configuration
      7. 26.3.7 Periodic Alarm Configuration
      8. 26.3.8 Calibration
        1. 26.3.8.1 Crystal Offset Error
          1. 26.3.8.1.1 Offset Error Correction Mechanism
        2. 26.3.8.2 Crystal Temperature Error
          1. 26.3.8.2.1 Temperature Drift Correction Mechanism
      9. 26.3.9 RTC Events
        1. 26.3.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.9.2 Generic Event Publisher (GEN_EVENT)
    4. 26.4 RTC Registers
  29. 27WWDT
    1. 27.1 WWDT Overview
      1. 27.1.1 Watchdog Mode
      2. 27.1.2 Interval Timer Mode
    2. 27.2 WWDT Operation
      1. 27.2.1 Mode Selection
      2. 27.2.2 Clock Configuration
      3. 27.2.3 Low-Power Mode Behavior
      4. 27.2.4 Debug Behavior
      5. 27.2.5 WWDT Events
        1. 27.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 27.3 WWDT Registers
  30. 28Debug
    1. 28.1 Overview
      1. 28.1.1 Debug Interconnect
      2. 28.1.2 Physical Interface
      3. 28.1.3 Debug Access Ports
    2. 28.2 Debug Features
      1. 28.2.1 Processor Debug
        1. 28.2.1.1 Breakpoint Unit (BPU)
        2. 28.2.1.2 Data Watchpoint and Trace Unit (DWT)
        3. 28.2.1.3 Processor Trace (MTB)
      2. 28.2.2 Peripheral Debug
      3. 28.2.3 EnergyTrace Technology
    3. 28.3 Behavior in Low Power Modes
    4. 28.4 Restricting Debug Access
    5. 28.5 Mailbox (DSSM)
      1. 28.5.1 DSSM Events
        1. 28.5.1.1 CPU Interrupt Event (CPU_INT)
      2. 28.5.2 DEBUGSS Registers
  31. 29Revision History

1.5 NONMAIN Registers

Table 1-7 lists the memory-mapped registers for the NONMAIN registers. All register offset addresses not listed in Table 1-7 should be considered as reserved locations and the register contents should not be modified.

Table 1-7 NONMAIN Registers
OffsetAcronymRegister NameGroupSection
41C00000hBCRCONFIGIDConfiguration ID of BCR StructureGo
41C00004hBOOTCFG0Serial wire debug (SWD) lock policy.Go
41C00008hBOOTCFG1BSL invoke pin policy.Go
41C0000Ch + formulaPWDDEBUGLOCK[y]SWD command and password authentication request.Go
41C0001ChBOOTCFG2Fast boot mode policy and BSL mode policy.Go
41C00020hBOOTCFG3Mass erase and factory reset mode policies.
These policies affect SWD initiated and BSL initiated mass erase and factory reset commands.
If the SW-DP is disabled (SWDP_MODE is disabled), SWD initiated commands are not allowed as the SW-DP is fully disabled.
If the BSL is disabled (BSLMODE is disabled), these settings are a a don't care for BSL initiated commands as the BSL is not enabled to be invoked.		Go
41C00024h + formulaPWDMASSERASE[y]SWD mass erase command password (must be provided via DSSM to authenticate a mass erase command).Go
41C00034h + formulaPWDFACTORYRESET[y]SWD factory reset command password (must be provided via DSSM to authenticate a factory reset command).Go
41C00044hFLASHSWP0Static write protection policy for the first 32kB of flash memory.
When protected, sectors will not be available for program or erase by either the bootloader or application code.		Go
41C00048hFLASHSWP1Static write protection policy for additional sectors of flash memory.
When protected, sectors will not be available for program or erase by either the bootloader or application code.		Go
41C0004ChBOOTCFG4Go
41C00050hAPPCRCSTARTStart address of the application CRC check (must be an address in a MAIN flash region).Go
41C00054hAPPCRCLENGTHLength of the application area to include in the application CRC check (in bytes), starting from APPCRCSTART.Go
41C00058hAPPCRCExpected application CRC check digest (CRC-32) to test against during boot.Go
41C0005ChBOOTCRCCRC digest (CRC-32) of the BCR (boot configuration) portion of the NONMAIN memory.Go
41C00100hBSLCONFIGIDBSL configuration ID.Go
41C00104hBSLPINCFG0BSL UART pin configuration.Go
41C00108hBSLPINCFG1BSL I2C pin configuration.Go
41C0010ChBSLCONFIG0BSL invoke pin configuration and memory read-out policy.Go
41C00110h + formulaBSLPW[y]256-bit BSL access password.Go
41C00130hBSLPLUGINCFGDefines the presence and type of a BSL plug-in in MAIN flash memory.Go
41C00134h + formulaBSLPLUGINHOOK[y]Function pointers for plug-in init, receive, transmit, and de-init functions.Go
41C00144hPATCHHOOKIDAlternate BSL configuration.Go
41C00148hSBLADDRESSAddress of an alternate BSL.Go
41C0014ChBSLAPPVERAddress of the application version word.Go
41C00150hBSLCONFIG1BSL security configuration.Go
41C00154hBSLCRCCRC digest (CRC-32) of the BSL_CONFIG portion of the NONMAIN memory.Go

Complex bit access types are encoded to fit into small table cells. Table 1-8 shows the codes that are used for access types in this section.

Table 1-8 NONMAIN Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

1.5.1 BCRCONFIGID (Offset = 41C00000h) [Reset = 00000001h]

BCRCONFIGID is shown in Figure 1-2 and described in Table 1-9.

Return to the Summary Table.

Configuration ID of BCR Structure

Figure 1-2 BCRCONFIGID
313029282726252423222120191817161514131211109876543210
CONFIG
R/W-00000001h
Table 1-9 BCRCONFIGID Field Descriptions
BitFieldTypeResetDescription
31-0CONFIGR/W00000001hConfiguration ID of the BOOTCFG

1.5.2 BOOTCFG0 (Offset = 41C00004h) [Reset = AABBAABBh]

BOOTCFG0 is shown in Figure 1-3 and described in Table 1-10.

Return to the Summary Table.

Serial wire debug (SWD) lock policy.

Figure 1-3 BOOTCFG0
313029282726252423222120191817161514131211109876543210
SWDP_MODEDEBUGACCESS
R/W-AABBhW-AABBh
Table 1-10 BOOTCFG0 Field Descriptions
BitFieldTypeResetDescription
31-16SWDP_MODER/WAABBhThe serial wire debug port (SW-DP) access policy. This policy sets whether any communication is allowed with the device via the SWD pins (to any DAP). When disabled, no SWD communication is possible regardless of the configuration of the DEBUGACCESS field.
5566h = The SW-DP is fully disabled and no device access is possible via the SW-DP (0x5566 and all other values NOT 0xAABB).
AABBh = The SW-DP is enabled and device access is set by the additional policies in NONMAIN.
15-0DEBUGACCESSWAABBhThe debug access policy for accessing the AHB-AP, ET-AP, and PWR-AP debug access ports. Note that if SWDP_MODE is set to DISABLED, the value of this field is ignored and the debug port will remain fully locked.
5566h = Access to AHB-AP, ET-AP, and PWR-AP via SWD is disabled (0x5566 and all other values NOT 0xCCDD or 0xAABB).
AABBh = Access to AHB-AP, ET-AP, and PWR-AP via SWD is enabled.
CCDDh = Access to AHB-AP, ET-AP, and PWR-AP via SWD is only enabled when the correct password is provided via the DSSM before BCR execution.

1.5.3 BOOTCFG1 (Offset = 41C00008h) [Reset = AABBAABBh]

BOOTCFG1 is shown in Figure 1-4 and described in Table 1-11.

Return to the Summary Table.

BSL invoke pin policy.

Figure 1-4 BOOTCFG1
313029282726252423222120191817161514131211109876543210
BSL_PIN_INVOKETI_FA_MODE
R/W-AABBhR/W-AABBh
Table 1-11 BOOTCFG1 Field Descriptions
BitFieldTypeResetDescription
31-16BSL_PIN_INVOKER/WAABBhBoot strap loader (BSL) pin invoke method enable/disable policy.
5566h = The BSL_INVOKE pin is not checked during boot (0x5566 and all other values NOT 0xAABB).
AABBh = The BSL_INVOKE pin is checked during boot.
15-0TI_FA_MODER/WAABBhSets the TI failure analysis enable/disable policy. If enabled, a re-test request through DSSM is allowed, else it is not allowed. Note that if SWDP_MODE is set to disabled, this field is ignored and failure analysis is not possible.
5566h = TI failure analysis is not allowed (0x5566 and all other values NOT 0xAABB).
AABBh = TI failure analysis is allowed.

1.5.4 PWDDEBUGLOCK[y] (Offset = 41C0000Ch + formula) [Reset = FFFFFFFFh]

PWDDEBUGLOCK[y] is shown in Figure 1-5 and described in Table 1-12.

Return to the Summary Table.

SWD command and password authentication request.

Offset = 41C0000Ch + (y * 4h); where y = 0h to 3h

Figure 1-5 PWDDEBUGLOCK[y]
313029282726252423222120191817161514131211109876543210
PW
R/W-FFFFFFFFh
Table 1-12 PWDDEBUGLOCK[y] Field Descriptions
BitFieldTypeResetDescription
31-0PWR/WFFFFFFFFhPassword

1.5.5 BOOTCFG2 (Offset = 41C0001Ch) [Reset = AABBFFFFh]

BOOTCFG2 is shown in Figure 1-6 and described in Table 1-13.

Return to the Summary Table.

Fast boot mode policy and BSL mode policy.

Figure 1-6 BOOTCFG2
313029282726252423222120191817161514131211109876543210
BSLMODEFASTBOOTMODE
AABBhFFFFh
Table 1-13 BOOTCFG2 Field Descriptions
BitFieldTypeResetDescription
31-16BSLMODEAABBhBSLMODE configures the boot strap loader enable/disable policy.
5566h = The BSL is disabled (0x5566 and all other values NOT 0xAABB).
AABBh = The BSL is enabled.
15-0FASTBOOTMODEFFFFhFASTBOOTMODE configures the fast boot mode enable/disable policy.
5566h = Fast boot mode is disabled. All enabled BSL invoke conditions are evaluated (0x5566 and all other values NOT 0xAABB).
AABBh = Fast boot mode is enabled. Only the software BSL invoke condition is evaluated.

1.5.6 BOOTCFG3 (Offset = 41C00020h) [Reset = AABBAABBh]

BOOTCFG3 is shown in Figure 1-7 and described in Table 1-14.

Return to the Summary Table.

Mass erase and factory reset mode policies. These policies affect SWD initiated and BSL initiated mass erase and factory reset commands. If the SW-DP is disabled (SWDP_MODE is disabled), SWD initiated commands are not allowed as the SW-DP is fully disabled. If the BSL is disabled (BSLMODE is disabled), these settings are a a don't care for BSL initiated commands as the BSL is not enabled to be invoked.

Figure 1-7 BOOTCFG3
31302928272625242322212019181716
FACTORYRESETCMDACCESS
R/W-AABBh
1514131211109876543210
MASSERASECMDACCESS
R/W-AABBh
Table 1-14 BOOTCFG3 Field Descriptions
BitFieldTypeResetDescription
31-16FACTORYRESETCMDACCESSR/WAABBhThe factory reset command policy.
5566h = The factory reset command is not allowed (0x5566 and all other values NOT 0xAABB or 0xCCDD).
AABBh = The factory reset command is allowed.
CCDDh = The factory reset command is allowed only when the matching password is provided via the DSSM.
15-0MASSERASECMDACCESSR/WAABBhThe mass erase command policy.
5566h = The mass erase command is not allowed (0x5566 and all other values NOT 0xAABB or 0xCCDD).
AABBh = The mass erase command is allowed.
CCDDh = The mass erase command is allowed only when the matching password is provided via the DSSM.

1.5.7 PWDMASSERASE[y] (Offset = 41C00024h + formula) [Reset = FFFFFFFFh]

PWDMASSERASE[y] is shown in Figure 1-8 and described in Table 1-15.

Return to the Summary Table.

SWD mass erase command password (must be provided via DSSM to authenticate a mass erase command).

Offset = 41C00024h + (y * 4h); where y = 0h to 3h

Figure 1-8 PWDMASSERASE[y]
313029282726252423222120191817161514131211109876543210
PW
R/W-FFFFFFFFh
Table 1-15 PWDMASSERASE[y] Field Descriptions
BitFieldTypeResetDescription
31-0PWR/WFFFFFFFFhPassword

1.5.8 PWDFACTORYRESET[y] (Offset = 41C00034h + formula) [Reset = FFFFFFFFh]

PWDFACTORYRESET[y] is shown in Figure 1-9 and described in Table 1-16.

Return to the Summary Table.

SWD factory reset command password (must be provided via DSSM to authenticate a factory reset command).

Offset = 41C00034h + (y * 4h); where y = 0h to 3h

Figure 1-9 PWDFACTORYRESET[y]
313029282726252423222120191817161514131211109876543210
PW
R/W-FFFFFFFFh
Table 1-16 PWDFACTORYRESET[y] Field Descriptions
BitFieldTypeResetDescription
31-0PWR/WFFFFFFFFhPassword

1.5.9 FLASHSWP0 (Offset = 41C00044h) [Reset = FFFFFFFFh]

FLASHSWP0 is shown in Figure 1-10 and described in Table 1-17.

Return to the Summary Table.

Static write protection policy for the first 32kB of flash memory. When protected, sectors will not be available for program or erase by either the bootloader or application code.

Figure 1-10 FLASHSWP0
313029282726252423222120191817161514131211109876543210
MAINLOW
R/W-FFFFFFFFh
Table 1-17 FLASHSWP0 Field Descriptions
BitFieldTypeResetDescription
31-0MAINLOWR/WFFFFFFFFh1 bit per sector (Setting a bit to 0 disables write, 1 enables write).

1.5.10 FLASHSWP1 (Offset = 41C00048h) [Reset = FFFFFFFFh]

FLASHSWP1 is shown in Figure 1-11 and described in Table 1-18.

Return to the Summary Table.

Static write protection policy for additional sectors of flash memory. When protected, sectors will not be available for program or erase by either the bootloader or application code.

Figure 1-11 FLASHSWP1
313029282726252423222120191817161514131211109876543210
MAINHIGH
R/W-FFFFFFFFh
Table 1-18 FLASHSWP1 Field Descriptions
BitFieldTypeResetDescription
31-0MAINHIGHR/WFFFFFFFFh1 bit per 8 sectors. Bits 3:0, not used as covered with FLASHSWP0.(Setting a bit to 0 disables write, 1 enables write)

1.5.11 BOOTCFG4 (Offset = 41C0004Ch) [Reset = FFFFFFFFh]

BOOTCFG4 is shown in Figure 1-12 and described in Table 1-19.

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Figure 1-12 BOOTCFG4
3130292827262524
APPCRCMODE
R/W-FFFFh
2322212019181716
APPCRCMODE
R/W-FFFFh
15141312111098
RESERVED
R/W-
76543210
RESERVEDNONMAINSWP
R/W-R/W-FFFFh
Table 1-19 BOOTCFG4 Field Descriptions
BitFieldTypeResetDescription
31-16APPCRCMODER/WFFFFhAPPCRCMODE enables or disables the boot time CRC check of a segment of MAIN flash memory.
5566h = The boot time MAIN flash CRC check is disabled. The application code in MAIN flash is always started unless the reset vector or stack pointer are blank/unprogrammed (0x5566 and all other values NOT 0xAABB).
AABBh = The boot time MAIN flash CRC check is enabled. If the boot time CRC check passes, the application code in MAIN flash is started unless the reset vector or stack pointer are blank (unprogrammed). In the event of a failing CRC check, the application code in MAIN flash will not be started and the boot process fails.
15-1RESERVEDR/W0h
0NONMAINSWPR/WFFFFhStatic write protection policy for entire NONMAIN device configuration memory. Setting bit to 0 disables program/erase of the NONMAIN by all means other than a SWD-initiated factory reset, 1 enables program/erase of the NONMAIN by normal means.

1.5.12 APPCRCSTART (Offset = 41C00050h) [Reset = FFFFFFFFh]

APPCRCSTART is shown in Figure 1-13 and described in Table 1-20.

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Start address of the application CRC check (must be an address in a MAIN flash region).

Figure 1-13 APPCRCSTART
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-FFFFFFFFh
Table 1-20 APPCRCSTART Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WFFFFFFFFhApplication CRC check start address

1.5.13 APPCRCLENGTH (Offset = 41C00054h) [Reset = FFFFFFFFh]

APPCRCLENGTH is shown in Figure 1-14 and described in Table 1-21.

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Length of the application area to include in the application CRC check (in bytes), starting from APPCRCSTART.

Figure 1-14 APPCRCLENGTH
313029282726252423222120191817161514131211109876543210
LENGTH
R/W-FFFFFFFFh
Table 1-21 APPCRCLENGTH Field Descriptions
BitFieldTypeResetDescription
31-0LENGTHR/WFFFFFFFFhApplication CRC check source data length

1.5.14 APPCRC (Offset = 41C00058h) [Reset = FFFFFFFFh]

APPCRC is shown in Figure 1-15 and described in Table 1-22.

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Expected application CRC check digest (CRC-32) to test against during boot.

Figure 1-15 APPCRC
313029282726252423222120191817161514131211109876543210
DIGEST
R/W-FFFFFFFFh
Table 1-22 APPCRC Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/WFFFFFFFFhApplication CRC check expected digest.

1.5.15 BOOTCRC (Offset = 41C0005Ch) [Reset = 1879DAC3h]

BOOTCRC is shown in Figure 1-16 and described in Table 1-23.

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CRC digest (CRC-32) of the BCR (boot configuration) portion of the NONMAIN memory.

Figure 1-16 BOOTCRC
313029282726252423222120191817161514131211109876543210
DIGEST
R/W-1879DAC3h
Table 1-23 BOOTCRC Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/W1879DAC3hBCR boot configuration data CRC digest.

1.5.16 BSLCONFIGID (Offset = 41C00100h) [Reset = 00000001h]

BSLCONFIGID is shown in Figure 1-17 and described in Table 1-24.

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BSL configuration ID.

Figure 1-17 BSLCONFIGID
313029282726252423222120191817161514131211109876543210
CONFIG
R/W-00000001h
Table 1-24 BSLCONFIGID Field Descriptions
BitFieldTypeResetDescription
31-0CONFIGR/W00000001hConfiguration ID of the BSL_CONFIG.

1.5.17 BSLPINCFG0 (Offset = 41C00104h) [Reset = 02180217h]

BSLPINCFG0 is shown in Figure 1-18 and described in Table 1-25.

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BSL UART pin configuration.

Figure 1-18 BSLPINCFG0
31302928272625242322212019181716
UARTTX_MUX_SELUARTTX_PAD_NUM
R/W-02hR/W-18h
1514131211109876543210
UARTRX_MUX_SELUARTRX_PAD_NUM
R/W-02hR/W-17h
Table 1-25 BSLPINCFG0 Field Descriptions
BitFieldTypeResetDescription
31-24UARTTX_MUX_SELR/W02hUART TX IOMUX PINCM mux selection.
23-16UARTTX_PAD_NUMR/W18hUART TX IOMUX PINCM register.
15-8UARTRX_MUX_SELR/W02hUART RX IOMUX PINCM mux selection.
7-0UARTRX_PAD_NUMR/W17hUART RX IOMUX PINCM register.

1.5.18 BSLPINCFG1 (Offset = 41C00108h) [Reset = 03020301h]

BSLPINCFG1 is shown in Figure 1-19 and described in Table 1-26.

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BSL I2C pin configuration.

Figure 1-19 BSLPINCFG1
31302928272625242322212019181716
I2CSCL_MUX_SELI2CSCL_PAD_NUM
R/W-03hR/W-2h
1514131211109876543210
I2CSDA_MUX_SELI2CSDA_PAD_NUM
R/W-03hR/W-1h
Table 1-26 BSLPINCFG1 Field Descriptions
BitFieldTypeResetDescription
31-24I2CSCL_MUX_SELR/W03hI2C SCL IOMUX PINCM mux selection.
23-16I2CSCL_PAD_NUMR/W2hI2C SCL IOMUX PINCM register.
15-8I2CSDA_MUX_SELR/W03hI2C SDA IOMUX PINCM mux selection.
7-0I2CSDA_PAD_NUMR/W1hI2C SDA IOMUX PINCM register.

1.5.19 BSLCONFIG0 (Offset = 41C0010Ch) [Reset = FFFF1293h]

BSLCONFIG0 is shown in Figure 1-20 and described in Table 1-27.

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BSL invoke pin configuration and memory read-out policy.

Figure 1-20 BSLCONFIG0
3130292827262524
READOUTEN
R/W-FFFFh
2322212019181716
READOUTEN
R/W-FFFFh
15141312111098
RESERVEDBSLIVK_GPIOPORTBSLIVK_GPIOPIN
R-0hR/W-R/W-12h
76543210
BSLIVK_LVLRESERVEDBSLIVK_PAD_NUM
R/W-1hR-0hR/W-13h
Table 1-27 BSLCONFIG0 Field Descriptions
BitFieldTypeResetDescription
31-16READOUTENR/WFFFFhSets the memory read-out policy for the BSL interface.
5566h = Memory read-out is not possible via the BSL interface (0x5566 and all other values NOT 0xAABB).
AABBh = Memory contents may be read via the BSL interface.
15-14RESERVEDR0h
13BSLIVK_GPIOPORTR/W0hThe BSL_invoke GPIO port index corresponding to the pad used for BSL_invoke.
0h = The BSL_invoke pin is on GPIO port A.
1h = The BSL_invoke pin is on GPIO port B.
12-8BSLIVK_GPIOPINR/W12hThe BSL_invoke GPIO pin index corresponding to the pad used for BSL_invoke.
7BSLIVK_LVLR/W1hThe BSL_invoke input logic level which shall invoke the BSL.
0h = LOW
1h = HIGH
6RESERVEDR0h
5-0BSLIVK_PAD_NUMR/W13hThe IOMUX PINCM register corresponding to the pad to be used for BSL_invoke.

1.5.20 BSLPW[y] (Offset = 41C00110h + formula) [Reset = FFFFFFFFh]

BSLPW[y] is shown in Figure 1-21 and described in Table 1-28.

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256-bit BSL access password.

Offset = 41C00110h + (y * 4h); where y = 0h to 7h

Figure 1-21 BSLPW[y]
313029282726252423222120191817161514131211109876543210
PASSWORD
R/W-FFFFFFFFh
Table 1-28 BSLPW[y] Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORDR/WFFFFFFFFhPassword

1.5.21 BSLPLUGINCFG (Offset = 41C00130h) [Reset = FFFFFFFFh]

BSLPLUGINCFG is shown in Figure 1-22 and described in Table 1-29.

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Defines the presence and type of a BSL plug-in in MAIN flash memory.

Figure 1-22 BSLPLUGINCFG
31302928272625242322212019181716
SRAMEXISTSFLASHEXISTS
R/W-FFhR/W-FFh
1514131211109876543210
PLUGINTYPE
R/W-FFFFh
Table 1-29 BSLPLUGINCFG Field Descriptions
BitFieldTypeResetDescription
31-24SRAMEXISTSR/WFFhSRAM consumed by Flash plugin, from 0x00 to 0xFF.
23-16FLASHEXISTSR/WFFhThe field tells if Flash Plugin exists are not. 0xBB - Flash Plugin exists; 0xFF (all other values) - Only ROM plugins will be used.
15-0PLUGINTYPER/WFFFFhThe type code for the BSL plug-in.
1000h = Plug-in is for UART.
2000h = Plug-in is for I2C.
FFFFh = For all other values. Any other interfaces with valid hooks will be added to Plugin list.

1.5.22 BSLPLUGINHOOK[y] (Offset = 41C00134h + formula) [Reset = FFFFFFFFh]

BSLPLUGINHOOK[y] is shown in Figure 1-23 and described in Table 1-30.

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Function pointers for plug-in init, receive, transmit, and de-init functions.

Offset = 41C00134h + (y * 4h); where y = 0h to 3h

Figure 1-23 BSLPLUGINHOOK[y]
313029282726252423222120191817161514131211109876543210
BSLPLUGIN
R/W-FFFFFFFFh
Table 1-30 BSLPLUGINHOOK[y] Field Descriptions
BitFieldTypeResetDescription
31-0BSLPLUGINR/WFFFFFFFFhAddress of the BSL plug-in hook. Byte [3-0] : Init; Byte [7-4] : Receive; Byte [11-8] : Send; Byte [15-12] : Deinit

1.5.23 PATCHHOOKID (Offset = 41C00144h) [Reset = FFFFFFFFh]

PATCHHOOKID is shown in Figure 1-24 and described in Table 1-31.

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Alternate BSL configuration.

Figure 1-24 PATCHHOOKID
313029282726252423222120191817161514131211109876543210
RESERVEDID
R/W-R/W-FFFFFFFFh
Table 1-31 PATCHHOOKID Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0IDR/WFFFFFFFFhID field to invoke an alternate BSL.
5566h = Do not use an alternate BSL (0x5566 and all other values NOT 0xAABB).
AABBh = Use the alternate BSL.

1.5.24 SBLADDRESS (Offset = 41C00148h) [Reset = FFFFFFFFh]

SBLADDRESS is shown in Figure 1-25 and described in Table 1-32.

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Address of an alternate BSL.

Figure 1-25 SBLADDRESS
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-FFFFFFFFh
Table 1-32 SBLADDRESS Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WFFFFFFFFhAddress of the alternate BSL, if present.

1.5.25 BSLAPPVER (Offset = 41C0014Ch) [Reset = FFFFFFFFh]

BSLAPPVER is shown in Figure 1-26 and described in Table 1-33.

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Address of the application version word.

Figure 1-26 BSLAPPVER
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-FFFFFFFFh
Table 1-33 BSLAPPVER Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WFFFFFFFFhAddress of the application version word (must be a valid flash address to be returned).

1.5.26 BSLCONFIG1 (Offset = 41C00150h) [Reset = 0048FFFFh]

BSLCONFIG1 is shown in Figure 1-27 and described in Table 1-34.

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BSL security configuration.

Figure 1-27 BSLCONFIG1
313029282726252423222120191817161514131211109876543210
TARGETADDRALERTACTION
R/W-0048hR/W-FFFFh
Table 1-34 BSLCONFIG1 Field Descriptions
BitFieldTypeResetDescription
31-16TARGETADDRR/W0048hI2C target address to be used for the BSL I2C communication.
15-0ALERTACTIONR/WFFFFhAction to take upon a security alert condition.
5566h = Ignore the security alert condition (0x5566 and all other values NOT 0xAABB or 0xCCDD).
AABBh = Trigger a factory reset. Note that if sectors in MAIN or NONMAIN flash are write protected they will not be affected by the BSL factory reset.
CCDDh = Re-configure the NONMAIN region to disable the BSL. This is not supported if the NONMAIN region is configured to be write protected.

1.5.27 BSLCRC (Offset = 41C00154h) [Reset = 8C76DE95h]

BSLCRC is shown in Figure 1-28 and described in Table 1-35.

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CRC digest (CRC-32) of the BSL_CONFIG portion of the NONMAIN memory.

Figure 1-28 BSLCRC
313029282726252423222120191817161514131211109876543210
DIGEST
R/W-8C76DE95h
Table 1-35 BSLCRC Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/W8C76DE95hBSL configuration data CRC digest