SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
Table 19-1 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 19-1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
800h | PWREN | Power enable | Section 19.1 |
804h | RSTCTL | Reset Control | Section 19.2 |
808h | CLKCFG | Peripheral Clock Configuration Register | Section 19.3 |
814h | STAT | Status Register | Section 19.4 |
1000h | CLKDIV | Clock Divider | Section 19.5 |
1004h | CLKSEL | Clock Select for Ultra Low Power peripherals | Section 19.6 |
1018h | PDBGCTL | Peripheral Debug Control | Section 19.7 |
1020h | IIDX | Interrupt index | Section 19.8 |
1028h | IMASK | Interrupt mask | Section 19.9 |
1030h | RIS | Raw interrupt status | Section 19.10 |
1038h | MIS | Masked interrupt status | Section 19.11 |
1040h | ISET | Interrupt set | Section 19.12 |
1048h | ICLR | Interrupt clear | Section 19.13 |
1050h | IIDX | Interrupt index | Section 19.14 |
1058h | IMASK | Interrupt mask | Section 19.15 |
1060h | RIS | Raw interrupt status | Section 19.16 |
1068h | MIS | Masked interrupt status | Section 19.17 |
1070h | ISET | Interrupt set | Section 19.18 |
1078h | ICLR | Interrupt clear | Section 19.19 |
1080h | IIDX | Interrupt index | Section 19.20 |
1088h | IMASK | Interrupt mask | Section 19.21 |
1090h | RIS | Raw interrupt status | Section 19.22 |
1098h | MIS | Masked interrupt status | Section 19.23 |
10A0h | ISET | Interrupt set | Section 19.24 |
10A8h | ICLR | Interrupt clear | Section 19.25 |
10E0h | EVT_MODE | Event Mode | Section 19.26 |
10E4h | INTCTL | Interrupt control register | Section 19.27 |
10FCh | DESC | Module Description | Section 19.28 |
1200h | GFCTL | I2C Glitch Filter Control | Section 19.29 |
1204h | TIMEOUT_CTL | I2C Timeout Count Control Register | Section 19.30 |
1208h | TIMEOUT_CNT | I2C Timeout Count Register | Section 19.31 |
1210h | MSA | I2C Controller Target Address Register | Section 19.32 |
1214h | MCTR | I2C Controller Control Register | Section 19.33 |
1218h | MSR | I2C Controller Status Register | Section 19.34 |
121Ch | MRXDATA | I2C Controller RXData | Section 19.35 |
1220h | MTXDATA | I2C Controller TXData | Section 19.36 |
1224h | MTPR | I2C Controller Timer Period | Section 19.37 |
1228h | MCR | I2C Controller Configuration | Section 19.38 |
1234h | MBMON | I2C Controller Bus Monitor | Section 19.39 |
1238h | MFIFOCTL | I2C Controller FIFO Control | Section 19.40 |
123Ch | MFIFOSR | I2C Controller FIFO Status Register | Section 19.41 |
1250h | SOAR | I2C Target Own Address | Section 19.42 |
1254h | SOAR2 | I2C Target Own Address 2 | Section 19.43 |
1258h | SCTR | I2C Target Control Register | Section 19.44 |
125Ch | SSR | I2C Target Status Register | Section 19.45 |
1260h | SRXDATA | I2C Target RXData | Section 19.46 |
1264h | STXDATA | I2C Target TXData | Section 19.47 |
126Ch | SFIFOCTL | I2C Target FIFO Control | Section 19.48 |
1270h | SFIFOSR | I2C Target FIFO Status Register | Section 19.49 |
Complex bit access types are encoded to fit into small table cells. Table 19-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WK | W K |
Write Write protected by a key |
Reset or Default Value | ||
-n | Value after reset or the default value |
PWREN is shown in Figure 19-1 and described in Table 19-3.
Return to the Table 19-1.
Register to control the power state
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0h | R/WK-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to allow Power State Change 26h = KEY to allow write access to this register |
23-1 | RESERVED | R | 0h | |
0 | ENABLE | R/WK | 0h | Enable the power
#I2C_PERIPHERALREGION_EXT_GPRCM_GPRCM_PWREN_KEY must be set to 26h to write to this bit. 0h = Disable Power 1h = Enable Power |
RSTCTL is shown in Figure 19-2 and described in Table 19-4.
Return to the Table 19-1.
Register to control reset assertion and de-assertion
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETSTKYCLR | RESETASSERT | |||||
R-0h | WK-0h | WK-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | Unlock key B1h = KEY to allow write access to this register |
23-2 | RESERVED | R | 0h | |
1 | RESETSTKYCLR | WK | 0h | Clear the RESETSTKY bit in the STAT register
#I2C_PERIPHERALREGION_EXT_GPRCM_GPRCM_RSTCTL_KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Clear reset sticky bit |
0 | RESETASSERT | WK | 0h | Assert reset to the peripheral
#I2C_PERIPHERALREGION_EXT_GPRCM_GPRCM_RSTCTL_KEY must be set to B1h to write to this bit. 0h = Writing 0 has no effect 1h = Assert reset |
CLKCFG is shown in Figure 19-3 and described in Table 19-5.
Return to the Table 19-1.
Peripheral Clock Configuration Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BLOCKASYNC | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | W | 0h | KEY to Allow State Change -- 0xA9 A9h = key value to allow change field of GPRCM |
23-9 | RESERVED | R | 0h | |
8 | BLOCKASYNC | R/W | 0h | Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz 0h = Not block async clock request 1h = Block async clock request |
7-0 | RESERVED | R | 0h |
STAT is shown in Figure 19-4 and described in Table 19-6.
Return to the Table 19-1.
peripheral enable and reset status
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESETSTKY | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | |
16 | RESETSTKY | R | 0x0 | This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register 1h = The peripheral was reset since the last bit clear |
15-0 | RESERVED | R | 0h |
CLKDIV is shown in Figure 19-5 and described in Table 19-7.
Return to the Table 19-1.
This register is used to specify module-specific divide ratio of the functional clock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RATIO | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock 0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8 |
CLKSEL is shown in Figure 19-6 and described in Table 19-8.
Return to the Table 19-1.
Clock source selection.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSCLK_SEL | MFCLK_SEL | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | BUSCLK_SEL | R/W | 0h | Selects BUSCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
2 | MFCLK_SEL | R/W | 0h | Selects MFCLK as clock source if enabled 0h = Does not select this clock as a source 1h = Select this clock as a source |
1-0 | RESERVED | R | 0h |
PDBGCTL is shown in Figure 19-7 and described in Table 19-9.
Return to the Table 19-1.
This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1 | SOFT | R/W | 0h | Soft halt boundary control. This function is only available, if #I2C_PERIPHERALREGION_IPSTANDARD_PDBGCTL_FREE is set to 'STOP' 0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption |
0 | FREE | R/W | 0h | Free run control 0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted. 1h = The peripheral ignores the state of the Core Halted input |
IIDX is shown in Figure 19-8 and described in Table 19-10.
Return to the Table 19-1.
This register provides the highest priority enabled interrupt index.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = Controller data received 02h = Controller data transmitted 03h = Controller receive FIFO Trigger Level 04h = Controller transmit FIFO Trigger level 5h = RX FIFO FULL Event/interrupt pending 6h = Transmit FIFO/Buffer Empty Event/interrupt pending 08h = Address/Data NACK 09h = Start Event 0Ah = Stop Event 0Bh = Arbitration Lost Ch = DMA DONE on Channel TX Dh = DMA DONE on Channel RX Eh = Controller PEC Receive Error Event Fh = Timeout A Event 10h = Timeout B Event 11h = Target Data Event 12h = Target Data Event 13h = Target receive FIFO Trigger Level 14h = Target transmit FIFO Trigger level 15h = RX FIFO FULL Event/interrupt pending 16h = Transmit FIFO/Buffer Empty Event/interrupt pending 17h = Start Event 18h = Stop Event 19h = General Call Event 1Ah = DMA DONE on Channel TX 1Bh = DMA DONE on Channel RX 1Ch = Target PEC receive error event 1Dh = Target TX FIFO underflow 1Eh = Target RX FIFO overflow event 1Fh = Target arbitration lost event 20h = Interrupt overflow event |
IMASK is shown in Figure 19-9 and described in Table 19-11.
Return to the Table 19-1.
Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTR_OVFL | SARBLOST | SRX_OVFL | STX_UNFL | SPEC_RX_ERR | SDMA_DONE_RX | SDMA_DONE_TX | SGENCALL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SSTOP | SSTART | STXEMPTY | SRXFIFOFULL | STXFIFOTRG | SRXFIFOTRG | STXDONE | SRXDONE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TIMEOUTB | TIMEOUTA | MPEC_RX_ERR | MDMA_DONE_RX | MDMA_DONE_TX | MARBLOST | MSTOP | MSTART |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNACK | RESERVED | MTXEMPTY | MRXFIFOFULL | MTXFIFOTRG | MRXFIFOTRG | MTXDONE | MRXDONE |
R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INTR_OVFL | R/W | 0h | Interrupt Overflow Interrupt Mask 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
30 | SARBLOST | R/W | 0h | Target Arbitration Lost 0h = Clear Set Interrupt Mask 1h = Set Interrupt Mask |
29 | SRX_OVFL | R/W | 0h | Target RX FIFO overflow 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
28 | STX_UNFL | R/W | 0h | Target TX FIFO underflow 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
27 | SPEC_RX_ERR | R/W | 0h | Target RX Pec Error Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
26 | SDMA_DONE_RX | R/W | 0h | Target DMA Done on Event Channel RX 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
25 | SDMA_DONE_TX | R/W | 0h | Target DMA Done on Event Channel TX 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
24 | SGENCALL | R/W | 0h | General Call Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
23 | SSTOP | R/W | 0h | Stop Condition Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
22 | SSTART | R/W | 0h | Start Condition Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
21 | STXEMPTY | R/W | 0h | Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
20 | SRXFIFOFULL | R/W | 0h | RXFIFO full event. This interrupt is set if an Target RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
19 | STXFIFOTRG | R/W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
18 | SRXFIFOTRG | R/W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
17 | STXDONE | R/W | 0h | Target Transmit Transaction completed Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
16 | SRXDONE | R/W | 0h | Target Receive Data Interrupt Signals that a byte has been received 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
15 | TIMEOUTB | R/W | 0h | Timeout B Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
14 | TIMEOUTA | R/W | 0h | Timeout A Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
13 | MPEC_RX_ERR | R/W | 0h | Controller RX Pec Error Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
12 | MDMA_DONE_RX | R/W | 0h | DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt Mask |
11 | MDMA_DONE_TX | R/W | 0h | DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt Mask |
10 | MARBLOST | R/W | 0h | Arbitration Lost Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
9 | MSTOP | R/W | 0h | STOP Detection Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
8 | MSTART | R/W | 0h | START Detection Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | MNACK | R/W | 0h | Address/Data NACK Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | RESERVED | R | 0h | |
5 | MTXEMPTY | R/W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | MRXFIFOFULL | R/W | 0h | RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3 | MTXFIFOTRG | R/W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | MRXFIFOTRG | R/W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXDONE | R/W | 0h | Controller Transmit Transaction completed Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXDONE | R/W | 0h | Controller Receive Transaction completed Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Figure 19-10 and described in Table 19-12.
Return to the Table 19-1.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTR_OVFL | SARBLOST | SRX_OVFL | STX_UNFL | SPEC_RX_ERR | SDMA_DONE_RX | SDMA_DONE_TX | SGENCALL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SSTOP | SSTART | STXEMPTY | SRXFIFOFULL | STXFIFOTRG | SRXFIFOTRG | STXDONE | SRXDONE |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TIMEOUTB | TIMEOUTA | MPEC_RX_ERR | MDMA_DONE_RX | MDMA_DONE_TX | MARBLOST | MSTOP | MSTART |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNACK | RESERVED | MTXEMPTY | MRXFIFOFULL | MTXFIFOTRG | MRXFIFOTRG | MTXDONE | MRXDONE |
R-0h | R-0h | R-0h | R-0h | R/W-0h | R/W-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INTR_OVFL | R | 0h | Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced 0h = Interrupt did not occur 1h = Interrupt occured |
30 | SARBLOST | R | 0h | Target Arbitration Lost 0h = Interrupt did not occur 1h = Interrupt occured |
29 | SRX_OVFL | R | 0x0 | Target RX FIFO overflow 0h = Interrupt did not occur 1h = Interrupt Occured |
28 | STX_UNFL | R | 0x0 | Target TX FIFO underflow 0h = Interrupt did not occur 1h = Interrupt occured |
27 | SPEC_RX_ERR | R | 0x0 | Target RX Pec Error Interrupt 0h = Interrupt did not occur 1h = Interrupt ocuured |
26 | SDMA_DONE_RX | R | 0x0 | DMA Done on Event Channel RX 0h = Clear interrupt 1h = Set interrupt |
25 | SDMA_DONE_TX | R | 0x0 | DMA Done on Event Channel TX 0h = Clear interrupt 1h = Set interrupt |
24 | SGENCALL | R | 0x0 | General Call Interrupt 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
23 | SSTOP | R | 0x0 | Stop Condition Interrupt 0h = Clear Interrupt 1h = Set interrupt |
22 | SSTART | R | 0x0 | Start Condition Interrupt 0h = Clear interrupt 1h = Set Interrupt |
21 | STXEMPTY | R | 0x0 | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Set Interrupt Mask |
20 | SRXFIFOFULL | R | 0x0 | RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
19 | STXFIFOTRG | R | 0x0 | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
18 | SRXFIFOTRG | R | 0x0 | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
17 | STXDONE | R | 0x0 | Target Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
16 | SRXDONE | R | 0x0 | Target Receive Data Interrupt Signals that a byte has been received 0h = Interrupt did not occur 1h = Set Interrupt Mask |
15 | TIMEOUTB | R | 0x0 | Timeout B Interrupt 0h = Interrupt did not occur 1h = Interrupt occured |
14 | TIMEOUTA | R | 0x0 | Timeout A Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
13 | MPEC_RX_ERR | R | 0x0 | Controller RX Pec Error Interrupt 0h = Interrupt did not occur 1h = Interrupt Occured |
12 | MDMA_DONE_RX | R | 0x0 | DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt Mask |
11 | MDMA_DONE_TX | R | 0x0 | DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt Mask |
10 | MARBLOST | R | 0x0 | Arbitration Lost Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
9 | MSTOP | R | 0x0 | STOP Detection Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
8 | MSTART | R | 0x0 | START Detection Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
7 | MNACK | R | 0x0 | Address/Data NACK Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
6 | RESERVED | R | 0h | |
5 | MTXEMPTY | R | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Set Interrupt Mask |
4 | MRXFIFOFULL | R | 0x0 | RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Interrupt did not occur 1h = Set Interrupt Mask |
3 | MTXFIFOTRG | R/W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | MRXFIFOTRG | R/W | 0x0 | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXDONE | R | 0x0 | Controller Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
0 | MRXDONE | R | 0x0 | Controller Receive Transaction completed Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
MIS is shown in Figure 19-11 and described in Table 19-13.
Return to the Table 19-1.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTR_OVFL | SARBLOST | SRX_OVFL | STX_UNFL | SPEC_RX_ERR | SDMA_DONE_RX | SDMA_DONE_TX | SGENCALL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SSTOP | SSTART | STXEMPTY | SRXFIFOFULL | STXFIFOTRG | SRXFIFOTRG | STXDONE | SRXDONE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TIMEOUTB | TIMEOUTA | MPEC_RX_ERR | MDMA_DONE_RX | MDMA_DONE_TX | MARBLOST | MSTOP | MSTART |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNACK | RESERVED | MTXEMPTY | MRXFIFOFULL | MTXFIFOTRG | MRXFIFOTRG | MTXDONE | MRXDONE |
R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INTR_OVFL | R/W | 0h | Interrupt overflow 0h = Interrupt did not occur 1h = Interrupt occured |
30 | SARBLOST | R/W | 0h | Target Arbitration Lost 0h = Clear interrupt mask 1h = Set interrupt mask |
29 | SRX_OVFL | R/W | 0h | Target RX FIFO overflow 0h = Clear interrupt mask 1h = Set interrupt mask |
28 | STX_UNFL | R/W | 0h | Target TX FIFO underflow 0h = Clear interrupt mask 1h = Set interrupt mask |
27 | SPEC_RX_ERR | R/W | 0h | Target RX Pec Error Interrupt 0h = Clear interrupt mask 1h = Set interrupt mask |
26 | SDMA_DONE_RX | R/W | 0h | DMA Done on Event Channel RX 0h = Clear MIS 1h = Set MIS |
25 | SDMA_DONE_TX | R/W | 0h | DMA Done on Event Channel TX 0h = Clear MIS 1h = Set MIS |
24 | SGENCALL | R/W | 0h | General Call Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
23 | SSTOP | R/W | 0h | Target STOP Detection Interrupt 0h = Clear MIS 1h = Set MIS |
22 | SSTART | R/W | 0h | Target START Detection Interrupt 0h = Clear MIS 1h = Set MIS |
21 | STXEMPTY | R/W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Set Interrupt Mask |
20 | SRXFIFOFULL | R/W | 0h | RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
19 | STXFIFOTRG | R/W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
18 | SRXFIFOTRG | R/W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
17 | STXDONE | R/W | 0h | Target Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
16 | SRXDONE | R/W | 0h | Target Receive Data Interrupt Signals that a byte has been received 0h = Interrupt did not occur 1h = Set Interrupt Mask |
15 | TIMEOUTB | R/W | 0h | Timeout B Interrupt 0h = Clear interrupt mask 1h = Set interrupt mask |
14 | TIMEOUTA | R/W | 0h | Timeout A Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
13 | MPEC_RX_ERR | R/W | 0h | Controller RX Pec Error Interrupt 0h = Clear interrupt mask 1h = Set interrupt mask |
12 | MDMA_DONE_RX | R/W | 0h | DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt Mask |
11 | MDMA_DONE_TX | R/W | 0h | DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt Mask |
10 | MARBLOST | R/W | 0h | Arbitration Lost Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
9 | MSTOP | R/W | 0h | STOP Detection Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
8 | MSTART | R/W | 0h | START Detection Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
7 | MNACK | R/W | 0h | Address/Data NACK Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
6 | RESERVED | R | 0h | |
5 | MTXEMPTY | R/W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Interrupt did not occur 1h = Set Interrupt Mask |
4 | MRXFIFOFULL | R/W | 0h | RXFIFO full event. This interrupt is set if the RX FIFO is full. 0h = Interrupt did not occur 1h = Set Interrupt Mask |
3 | MTXFIFOTRG | R/W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | MRXFIFOTRG | R/W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXDONE | R/W | 0h | Controller Transmit Transaction completed Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
0 | MRXDONE | R/W | 0h | Controller Receive Data Interrupt 0h = Interrupt did not occur 1h = Set Interrupt Mask |
ISET is shown in Figure 19-12 and described in Table 19-14.
Return to the Table 19-1.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set.
If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTR_OVFL | SARBLOST | SRX_OVFL | STX_UNFL | SPEC_RX_ERR | SDMA_DONE_RX | SDMA_DONE_TX | SGENCALL |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SSTOP | SSTART | STXEMPTY | SRXFIFOFULL | STXFIFOTRG | SRXFIFOTRG | STXDONE | SRXDONE |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TIMEOUTB | TIMEOUTA | MPEC_RX_ERR | MDMA_DONE_RX | MDMA_DONE_TX | MARBLOST | MSTOP | MSTART |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNACK | RESERVED | MTXEMPTY | MRXFIFOFULL | MTXFIFOTRG | MRXFIFOTRG | MTXDONE | MRXDONE |
W-0h | R-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INTR_OVFL | W | 0h | Interrupt overflow 0h = No effect 1h = Set interrupt |
30 | SARBLOST | W | 0h | Target Arbitration Lost 0h = Writing 0 has no effect 1h = Set interrupt |
29 | SRX_OVFL | W | 0h | Target RX FIFO overflow 0h = Writing 0 has no effect 1h = Set interrupt |
28 | STX_UNFL | W | 0h | Target TX FIFO underflow 0h = Writing 0 has no effect 1h = Set interrupt |
27 | SPEC_RX_ERR | W | 0h | Target RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Set interrupt |
26 | SDMA_DONE_RX | W | 0h | DMA Done on Event Channel RX 0h = Writing 0 has no effect 1h = Set interrupt |
25 | SDMA_DONE_TX | W | 0h | DMA Done on Event Channel TX 0h = Writing 0 has no effect 1h = Set interrupt |
24 | SGENCALL | W | 0h | General Call Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
23 | SSTOP | W | 0h | Stop Condition Interrupt 0h = Writing 0 has no effect 1h = Set interrupt |
22 | SSTART | W | 0h | Start Condition Interrupt 0h = Writing 0 has no effect 1h = Set interrupt |
21 | STXEMPTY | W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
20 | SRXFIFOFULL | W | 0h | RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
19 | STXFIFOTRG | W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
18 | SRXFIFOTRG | W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
17 | STXDONE | W | 0h | Target Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
16 | SRXDONE | W | 0h | Target Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
15 | TIMEOUTB | W | 0h | Timeout B Interrupt 0h = Writing 0 has no effect 1h = Set interrupt |
14 | TIMEOUTA | W | 0h | Timeout A interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
13 | MPEC_RX_ERR | W | 0h | Controller RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Set interrupt |
12 | MDMA_DONE_RX | W | 0h | DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt Mask |
11 | MDMA_DONE_TX | W | 0h | DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt Mask |
10 | MARBLOST | W | 0h | Arbitration Lost Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
9 | MSTOP | W | 0h | STOP Detection Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
8 | MSTART | W | 0h | START Detection Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
7 | MNACK | W | 0h | Address/Data NACK Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
6 | RESERVED | R | 0h | |
5 | MTXEMPTY | W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
4 | MRXFIFOFULL | W | 0h | RXFIFO full event. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
3 | MTXFIFOTRG | W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | MRXFIFOTRG | W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXDONE | W | 0h | Controller Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
0 | MRXDONE | W | 0h | Controller Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
ICLR is shown in Figure 19-13 and described in Table 19-15.
Return to the Table 19-1.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTR_OVFL | SARBLOST | SRX_OVFL | STX_UNFL | SPEC_RX_ERR | SDMA_DONE_RX | SDMA_DONE_TX | SGENCALL |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SSTOP | SSTART | STXEMPTY | SRXFIFOFULL | STXFIFOTRG | SRXFIFOTRG | STXDONE | SRXDONE |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TIMEOUTB | TIMEOUTA | MPEC_RX_ERR | MDMA_DONE_RX | MDMA_DONE_TX | MARBLOST | MSTOP | MSTART |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNACK | RESERVED | MTXEMPTY | MRXFIFOFULL | MTXFIFOTRG | MRXFIFOTRG | MTXDONE | MRXDONE |
W-0h | R-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | INTR_OVFL | W | 0h | Interrupt overflow 0h = No effect 1h = Clear interrupt |
30 | SARBLOST | W | 0h | Target Arbitration Lost 0h = Writing 0 has no effect 1h = Clear Interrupt |
29 | SRX_OVFL | W | 0h | Target RX FIFO overflow 0h = Writing 0 has no effect 1h = Clear Interrupt |
28 | STX_UNFL | W | 0h | Target TX FIFO underflow 0h = Writing 0 has no effect 1h = Clear Interrupt |
27 | SPEC_RX_ERR | W | 0h | Target RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt |
26 | SDMA_DONE_RX | W | 0h | DMA Done on Event Channel RX 0h = Writing 0 has no effect 1h = Clear interrupt |
25 | SDMA_DONE_TX | W | 0h | DMA Done on Event Channel TX 0h = Writing 0 has no effect 1h = Clear interrupt |
24 | SGENCALL | W | 0h | General Call Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
23 | SSTOP | W | 0h | Target STOP Detection Interrupt 0h = Writing 0 has no effect 1h = Clear interrupt |
22 | SSTART | W | 0h | Target START Detection Interrupt 0h = Writing 0 has no effect 1h = Clear interrupt |
21 | STXEMPTY | W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
20 | SRXFIFOFULL | W | 0h | RXFIFO full event. This interrupt is set if an RX FIFO is full. 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
19 | STXFIFOTRG | W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
18 | SRXFIFOTRG | W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
17 | STXDONE | W | 0h | Target Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
16 | SRXDONE | W | 0h | Target Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
15 | TIMEOUTB | W | 0h | Timeout B Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt |
14 | TIMEOUTA | W | 0h | Timeout A interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
13 | MPEC_RX_ERR | W | 0h | Controller RX Pec Error Interrupt 0h = Writing 0 has no effect 1h = Clear Interrupt |
12 | MDMA_DONE_RX | W | 0h | DMA Done on Event Channel RX 0h = Interrupt disabled 1h = Set Interrupt Mask |
11 | MDMA_DONE_TX | W | 0h | DMA Done on Event Channel TX 0h = Interrupt disabled 1h = Set Interrupt Mask |
10 | MARBLOST | W | 0h | Arbitration Lost Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
9 | MSTOP | W | 0h | STOP Detection Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
8 | MSTART | W | 0h | START Detection Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
7 | MNACK | W | 0h | Address/Data NACK Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
6 | RESERVED | R | 0h | |
5 | MTXEMPTY | W | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
4 | MRXFIFOFULL | W | 0h | RXFIFO full event. 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
3 | MTXFIFOTRG | W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | MRXFIFOTRG | W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXDONE | W | 0h | Controller Transmit Transaction completed Interrupt 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
0 | MRXDONE | W | 0h | Controller Receive Data Interrupt Signals that a byte has been received 0h = Writing 0 has no effect 1h = Set Interrupt Mask |
IIDX is shown in Figure 19-14 and described in Table 19-16.
Return to the Table 19-1.
This register provides the highest priority enabled interrupt index.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = Controller receive FIFO Trigger Level 02h = Controller transmit FIFO Trigger level 03h = Target receive FIFO Trigger Level 04h = Target transmit FIFO Trigger level |
IMASK is shown in Figure 19-15 and described in Table 19-17.
Return to the Table 19-1.
Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R/W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R/W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R/W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R/W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Figure 19-16 and described in Table 19-18.
Return to the Table 19-1.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R/W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R/W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R/W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R/W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
MIS is shown in Figure 19-17 and described in Table 19-19.
Return to the Table 19-1.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
ISET is shown in Figure 19-18 and described in Table 19-20.
Return to the Table 19-1.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set.
If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
ICLR is shown in Figure 19-19 and described in Table 19-21.
Return to the Table 19-1.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | W-0h | W-0h | W-0h | W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | W | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | W | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | W | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | W | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
IIDX is shown in Figure 19-20 and described in Table 19-22.
Return to the Table 19-1.
This register provides the highest priority enabled interrupt index.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | STAT | R | 0h | I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved 00h = No interrupt pending 01h = Controller receive FIFO Trigger Level 02h = Controller transmit FIFO Trigger level 03h = Target receive FIFO Trigger Level 04h = Target transmit FIFO Trigger level |
IMASK is shown in Figure 19-21 and described in Table 19-23.
Return to the Table 19-1.
Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Figure 19-22 and described in Table 19-24.
Return to the Table 19-1.
Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
MIS is shown in Figure 19-23 and described in Table 19-25.
Return to the Table 19-1.
Masked interrupt status. This is an AND of the IMASK and RIS registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
ISET is shown in Figure 19-24 and described in Table 19-26.
Return to the Table 19-1.
Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set.
If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
ICLR is shown in Figure 19-25 and described in Table 19-27.
Return to the Table 19-1.
Interrupt clear. Write a 1 to clear corresponding Interrupt.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STXFIFOTRG | SRXFIFOTRG | MTXFIFOTRG | MRXFIFOTRG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | |
3 | STXFIFOTRG | R | 0h | Target Transmit FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | SRXFIFOTRG | R | 0h | Target Receive FIFO Trigger 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | MTXFIFOTRG | R | 0h | Controller Transmit FIFO Trigger Trigger when Transmit FIFO contains <= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | MRXFIFOTRG | R | 0h | Controller Receive FIFO Trigger Trigger when RX FIFO contains >= defined bytes 0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
EVT_MODE is shown in Figure 19-26 and described in Table 19-28.
Return to the Table 19-1.
Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT2_CFG | INT1_CFG | INT0_CFG | ||||
R-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | |
5-4 | EVT2_CFG | R | 0h | Event line mode select for event corresponding to none.DMA_TRIG0 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
3-2 | INT1_CFG | R | 0h | Event line mode select for event corresponding to none.DMA_TRIG1 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
1-0 | INT0_CFG | R | 0h | Event line mode select for event corresponding to none.CPU_INT 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag. |
INTCTL is shown in Figure 19-27 and described in Table 19-29.
Return to the Table 19-1.
Interrupt control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTEVAL | ||||||
R-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | |
0 | INTEVAL | W | 0h | Writing a 1 to this field re-evaluates the interrupt sources. 0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. |
DESC is shown in Figure 19-28 and described in Table 19-30.
Return to the Table 19-1.
This register identifies the peripheral and its exact version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULEID | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEATUREVER | INSTNUM | MAJREV | MINREV | ||||||||||||
R-0h | R/W-0h | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R/W | 0h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. 0h = Smallest value FFFFh = Highest possible value |
15-12 | FEATUREVER | R | 0x0 | Feature Set for the module *instance* 0h = Smallest value Fh = Highest possible value |
11-8 | INSTNUM | R/W | 0x0 | Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances 0h = Smallest value Fh = Highest possible value |
7-4 | MAJREV | R | 0h | Major rev of the IP 0h = Smallest value Fh = Highest possible value |
3-0 | MINREV | R | 0x0 | Minor rev of the IP 0h = Smallest value Fh = Highest possible value |
GFCTL is shown in Figure 19-29 and described in Table 19-31.
Return to the Table 19-1.
This register controls the glitch filter on the SCL and SDA lines
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHAIN | AGFSEL | AGFEN | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DGFSEL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | |
11 | CHAIN | R/W | 0h | Analog and digital noise filters chaining enable. 0h = When 0, chaining is disabled and only digital filter output is available to IP logic for oversampling 1h = When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for oversampling |
10-9 | AGFSEL | R/W | 0h | Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only) 0h = Pulses shorter then 5ns length are filtered. 1h = Pulses shorter then 10ns length are filtered. 2h = Pulses shorter then 25ns length are filtered. 3h = Pulses shorter then 50ns length are filtered. |
8 | AGFEN | R/W | 0h | Analog Glitch Suppression Enable 0h = Analog Glitch Filter disable 1h = Analog Glitch Filter enable |
7-3 | RESERVED | R | 0h | |
2-0 | DGFSEL | R/W | 0x0 | Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only) 0h = Bypass 1h = 1 clock 2h = 2 clocks 3h = 3 clocks 4h = 4 clocks 5h = 8 clocks 6h = 16 clocks 7h = 31 clocks |
TIMEOUT_CTL is shown in Figure 19-30 and described in Table 19-32.
Return to the Table 19-1.
This register contains controls for Timeout Counters A and B
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TCNTBEN | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TCNTLB | |||||||
R/W-2h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TCNTAEN | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCNTLA | |||||||
R/W-2h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TCNTBEN | R/W | 0h | Timeout Counter B Enable 0h = Disable Timeout Counter B 1h = Enable Timeout Counter B |
30-24 | RESERVED | R | 0h | |
23-16 | TCNTLB | R/W | 2h | Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns. 0h = Smallest possible value FFh = Highest possible value |
15 | TCNTAEN | R/W | 0h | Timeout Counter A Enable 0h = Disable Timeout Counter B 1h = Enable Timeout Counter B |
14-8 | RESERVED | R | 0h | |
7-0 | TCNTLA | R/W | 2h | Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us. 0h = Smallest Value FFh = Highest possible value |
TIMEOUT_CNT is shown in Figure 19-31 and described in Table 19-33.
Return to the Table 19-1.
This register contains the upper 8 bits of a 12-bit current counter values for counter A and B. The lower four bits of the counter are not user visible and are always 0h.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCNTB | RESERVED | TCNTA | ||||||||||||||||||||||||||||
R-0h | R-2h | R-0h | R-2h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | |
23-16 | TCNTB | R | 2h | Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B 0h = Smallest Value FFh = Highest possible value |
15-8 | RESERVED | R | 0h | |
7-0 | TCNTA | R | 2h | Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A 0h = Smallest Value FFh = Highest possible value |
MSA is shown in Figure 19-32 and described in Table 19-34.
Return to the Table 19-1.
I2C Controller Target Address Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MMODE | RESERVED | SADDR | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SADDR | DIR | ||||||
R/W-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15 | MMODE | R/W | 0h | This bit selects the adressing mode to be used in Controller mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0h = 7-bit addressing mode 1h = 10-bit addressing mode |
14-11 | RESERVED | R | 0h | |
10-1 | SADDR | R/W | 0h | I2C Target Address This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care 0h = Smallest value 3FFh = Highest possible value |
0 | DIR | R | 0h | Receive/Send The DIR bit specifies if the next Controller operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive 0h = The Controller is in transmit mode. 1h = The Controller is in receive mode. |
MCTR is shown in Figure 19-33 and described in Table 19-35.
Return to the Table 19-1.
This control register configures the I2C controller operation. The START bit generates the START or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle or continues to the next transfer cycle, which could be a repeated START. To generate a single transmit cycle, the I2C Controller Target Address (MSA) register is written with the desired address, the RS bit is cleared, and this register is written with ACK = X (0 or 1), STOP = 1, START = 1, and RUN = 1 to perform the operation and stop. When the operation is completed (or aborted due an error), an byte transaction completed interrupt becomes active and the data may be read from the MRXDATA register. When the I2C module operates in Controller receiver mode, a set ACK bit causes the I2C bus controller to transmit an acknowledge automatically after each byte. This bit must be cleared when the I2C bus controller requires no further data to be transmitted from the Target transmitter.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | MBLEN | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MBLEN | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RD_ON_TXEMPTY | MACKOEN | ACK | STOP | START | BURSTRUN | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | |
27-16 | MBLEN | R/W | 0h | I2C transaction length This field contains the programmed length of bytes of the Transaction. 0h = Smallest value FFFh = Highest possible value |
15-6 | RESERVED | R | 0h | |
5 | RD_ON_TXEMPTY | R/W | 0h | Read on TX Empty 0h = No special behavior 1h = When 1 the Controller will transmit all bytes from the TX FIFO before continuing with the programmed Burst Run Read. If the DIR is not set to Read in the MSA then this bit is ignored. The Start must be set in the MCTR for proper I2C protocol. The Controller will first send the Start Condition, I2C Address with R/W bit set to write, before sending the bytes in the TX FIFO. When the TX FIFO is empty, the I2C transaction will continue as programmed in MTCR and MSA without sending a Stop Condition. This is intended to be used to perform simple I2C command based reads transition that will complete after initiating them without having to get an interrupt to turn the bus around. |
4 | MACKOEN | R/W | 0h | Controller ACK overrride Enable 0h = No special behavior 1h = When 1 and the Controller is receiving data and the number of bytes indicated in MBLEN have been received, the state machine will generate an rxdone interrupt and wait at the start of the ACK for FW to indicate if an ACK or NACK should be sent. The ACK or NACK is selected by writing the MCTR register and setting ACK accordingly. The other fields in this register can also be written at this time to continue on with the transaction. If a NACK is sent the state machine will automatically send a Stop. |
3 | ACK | R/W | 0h | Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. 0h = The last received data byte of a transaction is not acknowledged automatically by the Controller. 1h = The last received data byte of a transaction is acknowledged automatically by the Controller. |
2 | STOP | R/W | 0h | Generate STOP 0h = The controller does not generate the STOP condition. 1h = The controller generates the STOP condition. |
1 | START | R/W | 0h | Generate START 0h = The controller does not generate the START condition. 1h = The controller generates the START or repeated START condition. |
0 | BURSTRUN | R/W | 0h | I2C Controller Enable and start transaction 0h = In standard mode, this encoding means the Controller is unable to transmit or receive data. 1h = The Controller is able to transmit or receive data. |
MSR is shown in Figure 19-34 and described in Table 19-36.
Return to the Table 19-1.
The status register indicates the state of the I2C bus controller.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | MBCNT | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MBCNT | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BUSBSY | IDLE | ARBLST | DATACK | ADRACK | ERR | BUSY |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | |
27-16 | MBCNT | R | 0x0 | I2C Controller Transaction Count This field contains the current count-down value of the transaction. 0h = Smallest value FFFh = Highest possible value |
15-7 | RESERVED | R | 0h | |
6 | BUSBSY | R | 0x0 | I2C Bus is Busy Controller State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. 0h = The I2C bus is idle. 1h = 'This Status bit is set on a START or when SCL goes low. It is cleared on a STOP, or when a SCL high bus busy timeout occurs and SCL and SDA are both high. This status is cleared when the ACTIVE bit is low. Note that the Controller State Machine will wait until this bit is cleared before starting an I2C transaction. When first enabling the Controller in multi Controller environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY. |
5 | IDLE | R | 0h | I2C Idle 0h = The I2C controller is not idle. 1h = The I2C controller is idle. |
4 | ARBLST | R | 0x0 | Arbitration Lost 0h = The I2C controller won arbitration. 1h = The I2C controller lost arbitration. |
3 | DATACK | R | 0x0 | Acknowledge Data 0h = The transmitted data was acknowledged 1h = The transmitted data was not acknowledged. |
2 | ADRACK | R | 0x0 | Acknowledge Address 0h = The transmitted address was acknowledged 1h = The transmitted address was not acknowledged. |
1 | ERR | R | 0x0 | Error The error can be from the Target address not being acknowledged or the transmit data not being acknowledged. 0h = No error was detected on the last operation. 1h = An error occurred on the last operation. |
0 | BUSY | R | 0x0 | I2C Controller FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction. 0h = The controller is idle. 1h = The controller is busy. |
MRXDATA is shown in Figure 19-35 and described in Table 19-37.
Return to the Table 19-1.
I2C Controller RX FIFO Read Data Byte
This field contains the current byte being read in the RX FIFO stack.
If the FIFO is disabled,
the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | VALUE | R | 0h | Received Data. This field contains the last received data. 0h = Smallest value FFh = Highest possible value |
MTXDATA is shown in Figure 19-36 and described in Table 19-38.
Return to the Table 19-1.
I2C Controller Transmit Data Register.
This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data
written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | VALUE | R/W | 0h | Transmit Data This byte contains the data to be transferred during the next transaction. 0h = Smallest value FFh = Highest possible value |
MTPR is shown in Figure 19-37 and described in Table 19-39.
Return to the Table 19-1.
This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard mode.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TPR | ||||||||||||||||||||||||||||||
R-0h | R/W-1h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | |
6-0 | TPR | R/W | 1h | Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) × (SCL_LP + SCL_HP ) × INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns. 0h = Smallest value 7Fh = Highest possible value |
MCR is shown in Figure 19-38 and described in Table 19-40.
Return to the Table 19-1.
Controller configuration register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LPBK | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKSTRETCH | MMST | ACTIVE | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | |
8 | LPBK | R/W | 0h | I2C Loopback 0h = Normal operation. 1h = The controller in a test mode loopback configuration. |
7-3 | RESERVED | R | 0h | |
2 | CLKSTRETCH | R/W | 0h | Clock Stretching. This bit controls the support for clock stretching of the I2C bus. 0h = Disables the clock stretching detection. This can be disabled if no Target on the bus does support clock stretching, so that the maximum speed on the bus can be reached. 1h = Enables the clock stretching detection. Enabling the clock stretching ensures compliance to the I2C standard but could limit the speed due the clock stretching. |
1 | MMST | R/W | 0h | MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C
controller. 0h = Disable MultiController mode. 1h = Enable MultiController mode. |
0 | ACTIVE | R/W | 0h | Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur. 0h = Disables the I2C Controller operation. 1h = Enables the I2C Controller operation. |
MBMON is shown in Figure 19-39 and described in Table 19-41.
Return to the Table 19-1.
This register is used to determine the SCL and SDA signal status.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDA | SCL | |||||||||||||
R-0h | R-1h | R-1h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | |
1 | SDA | R | 1h | I2C SDA Status 0h = The I2CSDA signal is low. 1h = The I2CSDA signal is high. Note: During and right after reset, the SDA pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. |
0 | SCL | R | 1h | I2C SCL Status 0h = The I2CSCL signal is low. 1h = The I2CSCL signal is high. Note: During and right after reset, the SCL pin is in GPIO input mode without the internal pull enabled. For proper I2C operation, the user should have the external pull-up resistor in place before starting any I2C operations. |
MFIFOCTL is shown in Figure 19-40 and described in Table 19-42.
Return to the Table 19-1.
I2C Controller FIFO Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RXFLUSH | RESERVED | RXTRIG | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFLUSH | RESERVED | TXTRIG | |||||
R/W-0h | R-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15 | RXFLUSH | R/W | 0h | RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO |
14-11 | RESERVED | R | 0h | |
10-8 | RXTRIG | R/W | 0h | RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 0h = Trigger when RX FIFO contains >= 1 byte 1h = Trigger when RX FIFO contains >= 2 byte 2h = Trigger when RX FIFO contains >= 3 byte 3h = Trigger when RX FIFO contains >= 4 byte 4h = Trigger when RX FIFO contains >= 5 byte 5h = Trigger when RX FIFO contains >= 6 byte 6h = Trigger when RX FIFO contains >= 7 byte 7h = Trigger when RX FIFO contains >= 8 byte |
7 | TXFLUSH | R/W | 0h | TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO |
6-3 | RESERVED | R | 0h | |
2-0 | TXTRIG | R/W | 0h | TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 0h = Trigger when the TX FIFO is empty. 1h = Trigger when TX FIFO contains ≤ 1 byte 2h = Trigger when TX FIFO contains ≤ 2 byte 3h = Trigger when TX FIFO contains ≤ 3 byte 4h = Trigger when TX FIFO contains ≤ 4 byte 5h = Trigger when TX FIFO contains ≤ 5 byte 6h = Trigger when TX FIFO contains ≤ 6 byte 7h = Trigger when TX FIFO contains ≤ 7 byte |
MFIFOSR is shown in Figure 19-41 and described in Table 19-43.
Return to the Table 19-1.
I2C Controller FIFO Status Register
Note: this Register should only be read when BUSY is 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXFLUSH | RESERVED | TXFIFOCNT | |||||
R/W-0h | R-0h | R-8h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXFLUSH | RESERVED | RXFIFOCNT | |||||
R/W-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15 | TXFLUSH | R/W | 0h | TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0h = FIFO Flush not active 1h = FIFO Flush active |
14-12 | RESERVED | R | 0h | |
11-8 | TXFIFOCNT | R | 8h | Number of Bytes which could be put into the TX FIFO 0h = Smallest value 8h = Highest possible value |
7 | RXFLUSH | R/W | 0h | RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0h = FIFO Flush not active 1h = FIFO Flush active |
6-4 | RESERVED | R | 0h | |
3-0 | RXFIFOCNT | R | 0h | Number of Bytes which could be read from the RX FIFO 0h = Smallest value 8h = Highest possible value |
SOAR is shown in Figure 19-42 and described in Table 19-44.
Return to the Table 19-1.
This register consists of seven address bits that identify the I2C device on the I2C bus.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SMODE | OAREN | RESERVED | OAR | ||||
R/W-0h | R/W-1h | R-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OAR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15 | SMODE | R/W | 0h | This bit selects the adressing mode to be used in Target mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used. 0h = Enable 7-bit addressing 1h = Enable 10-bit addressing |
14 | OAREN | R/W | 1h | I2C Target Own Address Enable 0h = Disable OAR address 1h = Enable OAR address |
13-10 | RESERVED | R | 0h | |
9-0 | OAR | R/W | 0h | I2C Target Own Address: This field specifies bits A9 through A0 of the Target address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care 0h = Smallest value 3FFh = Highest possible value |
SOAR2 is shown in Figure 19-43 and described in Table 19-45.
Return to the Table 19-1.
This register consists of seven address bits that identify the alternate address for the I2C device on the I2C bus.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OAR2_MASK | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OAR2EN | OAR2 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | |
22-16 | OAR2_MASK | R/W | 0h | I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address. The bits with value ‘1’ in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a don’t care. 0h = Minimum Value 7Fh = Maximum Value |
15-8 | RESERVED | R | 0h | |
7 | OAR2EN | R/W | 0h | I2C Target Own Address 2 Enable 0h = The alternate address is disabled. 1h = Enables the use of the alternate address in the OAR2 field. |
6-0 | OAR2 | R/W | 0h | I2C Target Own Address 2 This field specifies the alternate OAR2 address. 0h = Smallest value 7Fh = Highest possible value |
SCTR is shown in Figure 19-44 and described in Table 19-46.
Return to the Table 19-1.
I2C Target Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWUEN | EN_DEFDEVADR | EN_ALRESPADR | ||||
R-0h | R/W-1h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_DEFHOSTADR | RXFULL_ON_RREQ | TXWAIT_STALE_TXFIFO | TXTRIG_TXMODE | TXEMPTY_ON_TREQ | SCLKSTRETCH | GENCALL | ACTIVE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-1h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | |
10 | SWUEN | R/W | 1h | Target Wakeup Enable 0h = When 0, the Target is not allowed to clock stretch on START detection 1h = When 1, the Target is allowed to clock stretch on START detection and wait for faster clock to be abvailable. This allows clean wake up support for I2C in low power mode use cases |
9 | EN_DEFDEVADR | R/W | 0h | Enable Deault device address 0h = When this bit is 0, the default device address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2. 1h = When this bit is 1, default device address of 7’h110_0001 is always matched by the Target address match logic. |
8 | EN_ALRESPADR | R/W | 0h | Enable Alert Response Address 0h = When this bit is 0, the alert response address is not matched. NOTE: it may still be matched if programmed inside SOAR/SOAR2 1h = When this bit is 1, alert response address of 7’h000_1100 is always matched by the Target address match logic. |
7 | EN_DEFHOSTADR | R/W | 0h | Enable Default Host Address 0h = When this bit is 0, the default host address is not matched NOTE: it may still be matched if programmed inside SOAR/SOAR2 1h = When this bit is 1, default host address of 7’h000_1000 is always matched by the Target address match logic. |
6 | RXFULL_ON_RREQ | R/W | 0h | Rx full interrupt generated on RREQ condition as indicated in SSR 0h = When 0, RIS:SRXFULL will be set when only the Target RX FIFO is full. This allows the SRXFULL interrupt to be used to indicate that the I2C bus is being clock stretched and that the FW must either read the RX FIFO or ACK/NACK the current Rx byte. 1h = When 1, RIS:SRXFULL will be set when the Target State Machine is in the RX_WAIT or RX_ACK_WAIT states which occurs when the I2C transaction is clock stretched because the RX FIFO is full or the ACKOEN has been set and the state machine is waiting for FW to ACK/NACK the current byte. |
5 | TXWAIT_STALE_TXFIFO | R/W | 0h | Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Target State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale. 0h = When 0, the TX FIFO empty signal to the Target State Machine indicates that the TX FIFO is empty. 1h = When 1, the TX FIFO empty signal to the Target State Machine will indicate that the TX FIFO is empty or that the TX FIFO data is stale. The TX FIFO data is determined to be stale when there is data in the TX FIFO when the Target State Machine leaves the TXMODE as defined in the SSR register. This can occur is a Stop or timeout occur when there are bytes left in the TX FIFO. |
4 | TXTRIG_TXMODE | R/W | 0h | Tx Trigger when Target FSM is in Tx Mode 0h = No special behavior 1h = When 1, RIS:TXFIFOTRG will be set when the Target TX FIFO has reached the trigger level AND the Target State Machine is in the TXMODE as defined in the SSR register. When cleared RIS:TXFIFOTRG will be set when the Target TX FIFO is at or above the trigger level. This setting can be used to hold off the TX DMA until a transaction starts. This allows the DMA to be configured when the I2C is idle but have it wait till the transaction starts to load the Target TX FIFO, so it can load from a memory buffer that might be changing over time. |
3 | TXEMPTY_ON_TREQ | R | 0h | Tx Empty Interrupt on TREQ 0h = When 0, RIS:STXEMPTY will be set when only the Target TX FIFO is empty. This allows the STXEMPTY interrupt to be used to indicate that the I2C bus is being clock stretched and that Target TX data is required. 1h = When 1, RIS:STXEMPTY will be set when the Target State Machine is in the TX_WAIT state which occurs when the TX FIFO is empty AND the I2C transaction is clock stretched waiting for the FIFO to receive data. |
2 | SCLKSTRETCH | R/W | 1h | Target Clock Stretch Enable 0h = Target clock stretching is disabled 1h = Target clock stretching is enabled |
1 | GENCALL | R/W | 0h | General call response enable Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call 0h = Do not respond to a general call 1h = Respond to a general call |
0 | ACTIVE | R/W | 0h | Device Active. Setting this bit enables the Target functionality. 0h = Disables the I2C Target operation. 1h = Enables the I2C Target operation. |
SSR is shown in Figure 19-45 and described in Table 19-47.
Return to the Table 19-1.
This register functions as a control register when written, and a status register when read.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADDRMATCH | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADDRMATCH | STALE_TXFIFO | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXMODE | BUSBSY | QCMDRW | QCMDST | OAR2SEL | RXMODE | TREQ | RREQ |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | |
18-9 | ADDRMATCH | R | 0h | Indicates the address for which Target address match happened 0h = Minimum Value 3FFh = Maximum Value |
8 | STALE_TXFIFO | R | 0h | Stale Tx FIFO 0h = Tx FIFO is not stale 1h = The TX FIFO is stale. This occurs when the TX FIFO was not emptied during the previous I2C transaction. |
7 | TXMODE | R | 0h | Target FSM is in TX MODE 0h = The Target State Machine is not in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. 1h = The Target State Machine is in TX_DATA, TX_WAIT, TX_ACK or ADDR_ACK state with the bus direction set to read. |
6 | BUSBSY | R | 0h | I2C bus is busy 0h = The I2C Bus is not busy 1h = The I2C Bus is busy. This is cleared on a timeout. |
5 | QCMDRW | R | 0h | Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read 0h = Quick command was a write 1h = Quick command was a read |
4 | QCMDST | R | 0h | Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction 0h = The last transaction was a normal transaction or a transaction has not occurred. 1h = The last transaction was a Quick Command transaction. |
3 | OAR2SEL | R | 0h | OAR2 Address Matched This bit gets reevaluated after every address comparison. 0h = Either the OAR2 address is not matched or the match is in legacy mode. 1h = OAR2 address matched and ACKed by the Target. |
2 | RXMODE | R | 0h | Target FSM is in Rx MODE 0h = The Target State Machine is not in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. 1h = The Target State Machine is in the RX_DATA, RX_ACK, RX_WAIT, RX_ACK_WAIT or ADDR_ACK state with the bus direction set to write. |
1 | TREQ | R | 0h | Transmit Request 0h = No outstanding transmit request. 1h = The I2C controller has been addressed as a Target transmitter and is using clock stretching to delay the Controller until data has been written to the STXDATA FIFO (Target TX FIFO is empty). |
0 | RREQ | R | 0h | Receive Request 0h = No outstanding receive data. 1h = The I2C controller has outstanding receive data from the I2C Controller and is using clock stretching to delay the Controller until the data has been read from the SRXDATA FIFO (Target RX FIFO is full). |
SRXDATA is shown in Figure 19-46 and described in Table 19-48.
Return to the Table 19-1.
I2C Target RX FIFO Read Data Byte
This field contains the current byte being read in the RX FIFO stack.
If the FIFO is disabled, the
data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | VALUE | R | 0h | Received Data. This field contains the last received data. 0h = Smallest value FFh = Highest possible value |
STXDATA is shown in Figure 19-47 and described in Table 19-49.
Return to the Table 19-1.
I2C Target Transmit Data Register.
This register is the transmit data register (the interface to the FIFOs). For transmitted data, if the FIFO is enabled, data
written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | |
7-0 | VALUE | R/W | 0h | Transmit Data This byte contains the data to be transferred during the next transaction. 0h = Smallest value FFh = Highest possible value |
SFIFOCTL is shown in Figure 19-48 and described in Table 19-50.
Return to the Table 19-1.
I2C Target FIFO Control
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RXFLUSH | RESERVED | RXTRIG | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFLUSH | RESERVED | TXTRIG | |||||
R/W-0h | R-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15 | RXFLUSH | R/W | 0h | RX FIFO Flush Setting this bit will Flush the RX FIFO. Before clearing this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO |
14-11 | RESERVED | R | 0h | |
10-8 | RXTRIG | R/W | 0h | RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO. 4h = Trigger when RX FIFO contains >= 5 byte 5h = Trigger when RX FIFO contains >= 6 byte 6h = Trigger when RX FIFO contains >= 7 byte 7h = Trigger when RX FIFO contains >= 8 byte |
7 | TXFLUSH | R/W | 0h | TX FIFO Flush Setting this bit will Flush the TX FIFO. Before clearing this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed. 0h = Do not Flush FIFO 1h = Flush FIFO |
6-3 | RESERVED | R | 0h | |
2-0 | TXTRIG | R/W | 0h | TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated. 4h = Trigger when TX FIFO contains ≤ 4 byte 5h = Trigger when TX FIFO contains ≤ 5 byte 6h = Trigger when TX FIFO contains ≤ 6 byte 7h = Trigger when TX FIFO contains ≤ 7 byte |
SFIFOSR is shown in Figure 19-49 and described in Table 19-51.
Return to the Table 19-1.
I2C Target FIFO Status Register
Note: this Register should only be read when BUSY is 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TXFLUSH | RESERVED | TXFIFOCNT | |||||
R/W-0h | R-0h | R-8h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXFLUSH | RESERVED | RXFIFOCNT | |||||
R/W-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15 | TXFLUSH | R/W | 0h | TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop. 0h = FIFO Flush not active 1h = FIFO Flush active |
14-12 | RESERVED | R | 0h | |
11-8 | TXFIFOCNT | R | 8h | Number of Bytes which could be put into the TX FIFO 0h = Smallest value 8h = Highest possible value |
7 | RXFLUSH | R/W | 0h | RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop. 0h = FIFOFlush not active 1h = FIFO Flush active |
6-4 | RESERVED | R | 0h | |
3-0 | RXFIFOCNT | R | 0h | Number of Bytes which could be read from the RX FIFO 0h = Smallest value 8h = Highest possible value |