SLAU846A June 2023 – October 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
The peripheral bus clock (ULPCLK) is asynchronous to the RTC clock source (RTCCLK). As a result, special care must be taken when reading and writing certain RTC peripheral registers.
The RTC counter/calendar registers are updated once per second. To prevent reading any counter/calendar register at the time of an update (which could result in an invalid time being read), a keep-out window is provided. The keep-out window is approximately 128/32768 seconds before the counters update. The read-only RTCRDY bit in the STA register is reset during the keep-out window, and set outside the keep-out window period. Any read of the counter/calendar registers while RTCRDY bit in the STA register is reset can potentially be invalid, and the time read should be ignored.
The RTCRDY interrupt mechanism can also be used to safely read the RTC counter/calendar registers. When the RTCRDY interrupt is enabled, an interrupt is generated based on the rising edge of the RTCRDY bit, causing the RTCRDY interrupt flag to be set. At this point, the application has nearly a complete second to safely read any or all of the RTC registers. To ensure a safe read, the RTCRDY bit in the STA register can be read again in the interrupt service routine and other interrupts can be disabled. This synchronization process prevents reading the time value during a counter/calendar transition. The RTCRDY interrupt flag is reset automatically when the interrupt is serviced, or can be reset by software.
The RTC counter/calendar registers can be written to at any time. Writes to the calendar registers take 2 to 3 RTCCLK cycles to take effect. If a back-to-back write is done on counter/calendar registers, then it is possible that for 2-3 RTCCLK cycles, the register is set to an undefined value. Therefore, back-to-back writes to calendar registers need to be avoided. Note that due to the synchronization, if a read immediately follows a write to the calendar registers, the read back value is always the actual counter value, which can be different than the written value due to the 2-3 RTCCLK cycles required to synchronize the newly written value.
The following registers are subject to the restrictions above: SEC, MIN, HOUR, DAY, MON, YEAR.
The RTC control register (CTL) can be read at any time. Writes to the CTL register should only be done when the TEV (interval timer) interrupt is disabled and after the RTCRDY interrupt is set.
The following register is subject to the restrictions above: CTL.
The RTC alarm configuration registers can be read at any time. Writes to the alarm registers must be done when the corresponding alarm interrupt is disabled, and after the RTCRDY interrupt is set.
The following registers are subject to the restrictions above: A1MIN, A1HOUR, A1DAY, A2MIN, A2HOUR, A2DAY.
The offset correction register (CAL) and temperature compensation register (TCMP) must only be written when the RTCTCRDY bit in the STA register is set. RTCTCRDY is a read-only bit which is set when the hardware is ready to take in new correction or compensation values. Writes applied when RTCTCRDY is cleared have no effect. The RTCTCOK status bit is provided in the STA register. If a write to CAL or TCMP was successful, RTCTCOK will be set, else it will be reset. RTCTCOK will hold its status until the next write attempt. If a write is unsuccessful, software needs to re-attempt the write when RTCTCRDY is set.
The following registers are subject to the restrictions above: TCMP, CAL.
The prescaler interval control registers can be read at any time. Writes to the prescaler control registers should only be done when the PS0 and PS1 interrupts are disabled.
The following registers are subject to the restrictions above: PSCTL.