SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The TIMx module provides 18 interrupt sources (depending on the specific TIMx module features) which can be configured to source a CPU interrupt event. The CPU interrupt event configuration is managed with the CPU_INT event management registers. Table 27-24 lists the CPU interrupt events from the TIMx in order of decreasing interrupt priority.
IIDX STAT | Name | Description | Timer Module |
---|---|---|---|
0x01 | Z | Zero event interrupt. This interrupt is set when there is a zero event. | TIMx |
0x02 | L | Load event interrupt. This interrupt is set when there is a load event. | TIMx |
0x05 | CCD0 | Capture or compare 0 down event. This interrupt is set when there is a down compare match event at CC0. | TIMx |
0x06 | CCD1 | Capture or compare 1 down event. This interrupt is set when there is a down compare match event at CC1. | TIMx |
0x07 | CCD2 | Capture or compare 2 down event. This interrupt is set when there is a down compare match event at CC2. This interrupt is only available for TIMA0. | TIMx |
0x08 | CCD3 | Capture or compare 3 down event. This interrupt is set when there is a down compare match event at CC3. This interrupt is only available for TIMA0. | TIMx |
0x09 | CCU0 | Capture or compare 0 up event. This interrupt is set when there is a up compare match event at CC0. | TIMx |
0x0A | CCU1 | Capture or compare 1 up event. This interrupt is set when there is a up compare match event at CC1. | TIMx |
0x0B | CCU2 | Capture or compare 2 up event. This interrupt is set when there is a up compare match event at CC2. | TIMx |
0x0C | CCU3 | Capture or compare 3 up event. This interrupt is set when there is a up compare match event at CC3. | TIMx |
0x0D | CCD4 | Capture or compare 4 down event. This interrupt is set when there is a down compare match event at CC4. This interrupt is only available for TIMA modules. | TIMA |
0x0E | CCD5 | Capture or compare 5 down event. This interrupt is set when there is a down compare match event at CC5. This interrupt is only available for TIMA modules. | TIMA |
0x0F | CCU4 | Capture or compare 4 up event. This interrupt is set when there is a up compare match event at CC4. This interrupt is only available for TIMA modules. | TIMA |
0x10 | CCU5 | Capture or compare 5 up event. This interrupt is set when there is a up compare match event at CC5. This interrupt is only available for TIMA modules. | TIMA |
0x19 | F | Fault event interrupt. This interrupt is set when there is a fault condition event. See Section 27.2.6. This interrupt is only available for TIMA modules with fault handler features. | TIMA |
0x1A | TOV | Trigger overflow interrupt. This interrupt is set if a trigger event is generated while the associated trigger channel is active. | TIMx |
0x1B | REPC | Repeat counter zero interrupt. This bit controls the generation of an interrupt if the repeat counter value transitions from a nonzero value to zero. This interrupt is only available for TIMA modules with a repeat counter feature. | TIMA |
0x1C | DC | Direction change interrupt, used in QEI mode. This interrupt is only available for TIMG modules with QEI features. | TIMG |
0X1D | QEIERR | Direction change interrupt, used in QEI mode. This interrupt is only available for TIMG modules with QEI features. | TIMG |
See Section 8.2.5 for guidance on configuring the event registers for CPU interrupts.