SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The DEBUGSS supports maintaining a debug connection through SWD in all operating modes except SHUTDOWN.
Access to device memory and peripherals is possible in RUN mode and SLEEP mode, in which a debug probe can be actively connected to the AHB-AP access port to interface with the processor. In STOP and STANDBY modes, a debug connection can be established and/or maintained with the DEBUGSS, but not with the CPU debug access port.
In SHUTDOWN mode, any active debug connection is terminated as the debug logic is powered down with the device VCORE. While a debug connection to the DEBUGSS is not possible while the device is in SHUTDOWN mode, a debug probe can cause the device to exit SHUTDOWN mode by attempting to communicate with the SWD pins. The device will detect attempted SWD communication even when the device is in SHUTDOWN. If activity is detected, a SHUTDOWN exit is initiated and the device will transition through a BOR state, after which a debug connection can be made to the DEBUGSS through SWD.
The DEBUGSS functionality by operating mode is given in Table 31-3.
Capability | RUN | SLEEP | STOP | STANDBY | SHUTDOWN | NRST HOLD |
---|---|---|---|---|---|---|
Processor debug | Y | Y | N | N | N | N |
Memory map access | Y | Y | N | N | N | N |
Debug status through SW-DP | Y | Y | Y | Y | N | Y |
Debug state maintained | Y | Y | Y | Y | N | N |
Wake from SWD | - | - | - | - | Y | - |