SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The DAC module provides different interrupt sources which can be configured to source a CPU interrupt event. In order of decreasing interrupt priority, the CPU interrupt events from the DAC are:
Index (IIDX) | Name | Description |
---|---|---|
0x0 | NO_INTR | No bit set (IIDX.STAT = 0) means there is no pending interrupt request |
0x2 | MODRDYIFG | The DAC output is settled after it is turned on using ENABLE in the CTL0 register |
0x9 | FIFOFULLIFG | FIFO full interrupt flag is set when the FIFO is full |
0xA | FIFO1B4IFG | FIFO one fourth empty interrupt flag is set when one fourth of FIFO locations are empty. |
0xB | FIFO1B2IFG | FIFO half empty interrupt flag is set when half of the FIFO locations are empty. |
0xC | FIFO3B4IFG | FIFO three fourth empty interrupt flag is set when all the locations in FIFO are empty. |
0xD | FIFOEMPTYIFG |
FIFO empty interrupt flag is set when all data in the FIFO have been shifted out. |
0xE | FIFOURUNIFG |
FIFO underrun flag is set when the FIFO read trigger is asserted while the FIFO is empty. |
0xF | DMADONEIFG |
DMA done interrupt flag is set when the DMA data transfer of programmed block size is completed |
The CPU interrupt event configuration is managed with the CPU_INT event management registers. Interrupt (RIS) flags are cleared upon software reading the IIDX register or writing to the respective ICLR register bits.
See Section 8.2.5 section for guidance on configuring the event registers for CPU interrupts.