SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
In TIMA only, the repeat counter (RC) is an 8-bit counter that provides the mechanism to suppress unnecessary events and generate real events for interrupt generation. Specifically, the repeat counter can suppress Load, Compare, and Zero events in the case where the timer is generating events that repeat for a known number of cycles, such a periodic PWM output waveform. This prevents generating excessive and unnecessary interrupts every timer period.
When the timer counter (TIMA.CTR) is advancing, the repeat counter (TIMA.RC) advances when the counter reloads (TIMA.CTR = 0). Software can set the how many timer counter reloads occur until generating the interrupts and events by setting the TIMA.RCLD register. When TIMA.RC = TIMA.RCLD, the repeat counter is reset back to zero and a Repeat Counter Zero event occurs (REPC) in the Interrupt and Event Status registers.
Additionally, the repeat counter provides the ability to suppress generation of Zero, Load, and Compare events when TIMA.RC does not equal zero.
Table 27-2 shows the repeat counter behavior with respect to the timer counter and repeat counter load value.
TIMA.CTR is Advancing (+1) | Counter value | TIMA.RC = TIMA.RCLD | Repeat Counter Behavior | Suppress Load and Zero Events (SLZERCNEZ = 1) | Suppress Compare Events (SCERCNEZ = 1) |
---|---|---|---|---|---|
No | - | - | Does not advance | Yes | Yes |
Yes | TIMA.CTR ≠ 0 | - | Does not advance | Yes | Yes |
Yes | TIMA.CTR = 0 | No | Advance (+1) | Yes | Yes |
Yes | TIMA.CTR = 0 | Yes | TIMA.RC = 0 | No | No |
Repeat counter example
As shown in Figure 27-3, the TIMA.CTR is configured for down-counting mode and zero events are generated once TIMA.CTR = 0. To suppress interrupt generation until 4 timer reloads occur, set TIMA.RCLD = 4 and TIMA.CTRCTL.SLZERCNEZ = 1 to suppress zero and load events until RC = 0 (which occurs once TIMA.RC = TIMA.RCLD).