The MCAN module performs CAN protocol
communication according to ISO 11898-1:2015. The bit rate can be programmed to
values up to 8Mbit/s. Additional transceiver hardware is required for the connection
to the physical layer (CAN bus).
For communication on a CAN network, individual message frames can be configured. The message frames and identifier masks are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the Message Handler.
The register set of the MCAN module can be accessed directly through the module interface. These registers are used to control and configure the CAN core and the Message Handler, and to access the Message RAM.
Figure 21-3 shows the MCAN module block diagram, followed by the description of the MCAN module blocks.
- CAN Core: The CAN core consists of the CAN protocol controller and the Rx/Tx shift register. It handles all ISO 11898-1:2015 protocol functions and supports 11-bit and 29-bit identifiers.
- Message Handler: the Message Handler (Rx Handler and Tx Handler) is a state machine that controls the data transfer between the single-ported Message RAM and the CAN core's Rx/Tx shift register. It also handles the acceptance filtering and Interrupt generation as programmed in the control registers.
- Message RAM: the main purpose of the Message RAM is to store Rx/Tx messages, Tx Event elements, and Message ID Filter elements (for more information, see Section 21.4.19).
- Message RAM Interface: enables a connection between the Message RAM and the other blocks in the MCAN module.
- Registers and Message Object Access: Data consistency is ensured by indirect accesses to the message objects. During normal operation, all software and DMA accesses to the Message RAM are done through interface registers. The interface registers have the same word-length as the Message RAM.
- Module Interface: The MCAN module registers are accessed by the user's software through a 32-bit peripheral bus interface.
- Clocking: Two clocks are provided to the MCAN module: the peripheral synchronous clock (interface clock - MCAN_ICLK) and the peripheral asynchronous clock (functional clock - MCAN_FCLK).
- Extension Interface: All selected internal status and control signals are routed to this interface (except for the indication signals of configuration change enable bit (MCAN_CCCR.CCE) and Interrupt Register bits (MCAN_IR).