SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
A generic route is a route in which the comparator peripheral publishing the event is configured to use one of several available generic route channels to publish its event to another entity (or entities, in the case of a splitter route), where an entity can be another peripheral, a generic DMA trigger event, or a generic CPU event.
The GEN_EVENT0 and GEN_EVENT1 registers are used to select a peripheral condition (Table 27-190) to use for publishing or subscribing an event. FPUB_0 and FPUB_1 are the publisher port registers and are used to configure which generic route channel to use to broadcast the event. FSUB_0 and FSUB_1 are the subscriber port registers and are used to configure which generic route channel to use to subscribe the event. Other peripherals, the DMA, or the CPU can subscribe to this event by configuring its subscriber port to listen on the same generic route channel which the publishing peripheral is connected to.
For example, through the use of a generic event channel, it is possible to directly start an ADC conversion from a TIMx event by connecting a TIMx FPUB_x and ADC FSUB_0 to the same generic event channel. Refer to Section 8.1.3.3 and Section 8.2.3 for how generic event route works.
IIDX STAT | Name | Description |
Timer Module |
---|---|---|---|
0x01 | Z | Zero event interrupt. This interrupt is set when there is a zero event. | TIMx |
0x02 | L | Load event interrupt. This interrupt is set when there is a load event. | TIMx |
0x05 | CCD0 | Capture or compare 0 down event. This interrupt is set when there is a down compare match event at CC0. | TIMx |
0x06 | CCD1 | Capture or compare 1 down event. This interrupt is set when there is a down compare match event at CC1. | TIMx |
0x07 | CCD2 | Capture or compare 2 down event. This interrupt is set when there is a down compare match event at CC2. This interrupt is only available for TIMA0. | TIMx |
0x08 | CCD3 | Capture or compare 3 down event. This interrupt is set when there is a down compare match event at CC3. This interrupt is only available for TIMA0. | TIMx |
0x09 | CCU0 | Capture or compare 0 up event. This interrupt is set when there is a up compare match event at CC0. | TIMx |
0x0A | CCU1 | Capture or compare 1 up event. This interrupt is set when there is a up compare match event at CC1. | TIMx |
0x0B | CCU2 | Capture or compare 2 up event. This interrupt is set when there is a up compare match event at CC2. | TIMx |
0x0C | CCU3 | Capture or compare 3 up event. This interrupt is set when there is a up compare match event at CC3. | TIMx |
0x0D |
CCD4 |
Capture or compare 4 down event. This interrupt is set when there is a down compare match event at CC4. This interrupt is only available for TIMA modules. | TIMA |
0x0E |
CCD5 |
Capture or compare 5 down event. This interrupt is set when there is a down compare match event at CC5. This interrupt is only available for TIMA modules. | TIMA |
0x0F |
CCU4 |
Capture or compare 4 up event. This interrupt is set when there is a up compare match event at CC4. This interrupt is only available for TIMA modules. | TIMA |
0x10 | CCU5 | Capture or compare 5 up event. This interrupt is set when there is a up compare match event at CC5. This interrupt is only available for TIMA modules. | TIMA |
0x19 | F | Fault event interrupt. This interrupt
is set when there is a fault condition event. See Section 27.2.6. This interrupt is only available for TIMA modules with fault handler features. |
TIMA |
0x1A | TOV | Trigger overflow interrupt. This interrupt is set if a trigger event is generated while the associated trigger channel is active. | TIMx |
0x1B | REPC | Repeat counter zero interrupt. This bit controls the generation of an interrupt if the repeat counter value transitions from a nonzero value to zero. This interrupt is only available for TIMA modules with a repeat counter feature. | TIMA |
0x1C | DC | Direction change interrupt, used in QEI mode. This interrupt is only available for TIMG modules with QEI features. | TIMG |
0x1D |
QEIERR |
Direction change interrupt, used in QEI mode. This interrupt is only available for TIMG modules with QEI features. | TIMG |
See Section 8.2.5 for guidance on configuring the event registers.