SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
It is possible to bypass the HFXT circuit and bring in a 4- to 48MHz typical frequency digital clock into the device to use as the HFCLK source instead of HFXT. To configure HFCLK to use a digital clock input instead of HFXT, first configure the IOMUX to enable the HFCLK_IN function on the appropriate pin. When IOMUX is configured correctly and the clock source is outputting a clock to HFCLK_IN, set the USEEXTHFCLK bit in the HSCLKEN register in SYSCTL.
To use HFCLK_IN as the PLL reference after selecting HFCLK_IN as the HFCLK source, set the SYSPLLREF bit in the SYSPLLCFG0 register in SYSCTL. If HFCLK_IN is selected as a reference for the SYSPLL (through HFCLK) and the SYSPLL is enabled, then the SYSPLL must be disabled and the SYSPLLOFF bit in the CLKSTATUS register must be set before the HFCLK_IN can be disabled by clearing the USEEXTHFCLK bit in HSCLKEN.
To source MCLK from HFCLK_IN after selecting HFCLK_IN as the HFCLK source, first set the HSCLKSEL bit in the HSCLKCFG register to select HFCLK as the high-speed clock source (rather than the system PLL output). Then, set the USEHSCLK bit in the MCLKCFG register to select the high-speed clock source as the MCLK source. Once USEHSCLK is set, HSCLKCFG must not change and the HFCLK_IN must not be disabled until the MCLK source is switched back to SYSOSC by clearing USEHSCLK and verifying that the HSCLKMUX bit in CLKSTATUS was cleared by hardware.
HFCLK_IN is compatible with digital square wave CMOS clock inputs and should have a typical duty cycle of 50%.