SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The UART module provides 18 interrupt sources which can be configured to source a CPU interrupt event. In order of decreasing interrupt priority, the CPU interrupt events from the UART are:
IIDX STAT | Name | Description |
---|---|---|
0x01 | RTOUT | UART receive timeout interrupt, This interrupt is asserted when the receive FIFO is not empty, and no further data is received specified time in the UARTx.IFLS.RXTOSEL bits. More information provided below. |
0x02 | FRMERR | UART framing error interrupt, see Section 18.2.3.6 for more information. |
0x03 | PARERR | UART parity error interrupt, see Section 18.2.3.6 for more information. |
0x04 | BRKERR | UART break error interrupt, see Section 18.2.3.6 for more information. |
0x05 | OVRERR | UART receive overrun error interrupt, see Section 18.2.3.6 for more information. |
0x06 | RXNE | Falling edge on RX interrupt, this interrupt triggers when there is a falling edge on RX line. |
0x07 | RXPE | Rising edge on RX interrupt, this interrupt triggers when there is a rising edge on RX line. |
0x08 | LINC0 | LIN capture 0 match interrupt, this interrupt triggers when the defined capture 0 value is reached in LIN counter. |
0x09 | LINC1 | LIN capture 1 match interrupt, this interrupt triggers when the defined capture 1 value is reached in LIN counter. |
0x0A | LINOVF | LIN counter overflow interrupt, this interrupt triggers when the 16bit LIN counter overflows. |
0x0B | RXINT | UART receive interrupt. More information provided below. |
0x0C | TXINT | UART transmit interrupt. More information provided below. |
0x0D | EOT | UART end of transmission interrupt, it indicates that the last bit of all transmitted data and status has left the serializer and without any further data in the TX FIFO. |
0x0E | ADDR_MATCH | Address match interrupt, used in protocols with address to indicate address match happened. |
0x0F | CTS | UART clear to send interrupt, indicate the CTS signal status. |
0x10 | DMA_DONE_RX | This interrupt is set if the RX DMA channel sends the DONE signal. |
0x11 | DMA_DONE_TX | This interrupt is set if the TX DMA channel sends the DONE signal. |
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received specified time in the IFLS.RXTOSEL bits. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), by reading the interrupt index from IIDX or when a 1 is written to the corresponding bit in the ICLR register.
The receive interrupt (RXINT, 0x0B) changes state when one of the following events occurs: