SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The I2C module provides 24 interrupt sources which can be configured to source a CPU interrupt event. In order of decreasing interrupt priority, the CPU interrupt events from the I2C are:
IIDX STAT | Name | Description |
---|---|---|
0x01 | MRXDONE | Controller receive transaction completed interrupt |
0x02 | MTXDONE | Controller transmit transaction completed interrupt |
0x03 | MRXFIFOTRG | Controller receive FIFO trigger. Trigger when RX FIFO contains >= defined bytes |
0x04 | MTXFIFOTRG | Controller transmit FIFO trigger. Trigger when Transmit FIFO contains <= defined bytes |
0x05 | MRXFIFOFULL | Controller RXFIFO full event. This interrupt is set if an RX FIFO is full. |
0x06 | MTXEMPTY | Controller transmit FIFO empty interrupt. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode. |
0x07 | MCLKTO | Controller clock timeout interrupt |
0x08 | MNACK | Address/Data NACK interrupt |
0x09 | MSTART | Controller START detection interrupt |
0x0A | MSTOP | Controller STOP detection interrupt |
0x0B | MARBLOST | Controller arbitration lost interrupt |
0x0C | MDMA_DONE_TX | Controller DMA TX done signal (see next section for more detail) |
0x0D | MDMA_DONE_RX | Controller DMA RX done signal (see next section for more detail) |
IIDX STAT | Name | Description |
---|---|---|
0x11 | SRXDONE | Target receive transaction completed interrupt |
0x12 | STXDONE | Target transmit transaction completed interrupt |
0x13 | SRXFIFOTRG | Target receive FIFO trigger. It will trigger when receive FIFO contains >= defined bytes |
0x14 | STXFIFOTRG | Target transmit FIFO trigger. It will trigger when transmit FIFO contains <= defined bytes |
0x15 | SXFIFOFULL | Target RXFIFO full event. This interrupt is set if an RX FIFO is full. |
0x16 | STXEMPTY | Target transmit FIFO empty interrupt. This interrupt is set if all data in the Target Transmit FIFO have been shifted out and the transmit goes into idle mode. |
0x17 | SSTART | Target START detection interrupt |
0x18 | SSTOP | Target STOP detection interrupt |
0x19 | SGENCALL | General call interrupt |
0x1A | SDMA_DONE_TX | Target DMA TX done signal (see next section for more detail) |
0x1B | SDMA_DONE_RX | Target DMA RX done signal (see next section for more detail) |
The CPU interrupt event configuration is managed with the CPU_INT event management registers. See Section 8.2.5 for guidance on configuring the Event registers for CPU interrupts.