SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The SYSPLL accepts an input reference clock from 4-48MHz. The available reference clocks include SYSOSC and HFCLK. The predivider PDIV scales the selected input reference clock ahead of the PLL feedback loop. PDIV can be selected as /1, /2, /4, or /8 by programming 0x0 to 0x3, respectively, into the PDIV field in the SYSPLLCFG1 register.
The effective divider can be calculated from the PDIV register setting as shown in Equation 6.
The PLL feedback loop sets the voltage controlled oscillator (VCO) output equal to the divided input reference clock fLOOPIN multiplied by the QDIV feedback divider. The QDIV divider is an integer divider with a valid range of /2 to /127. The desired QDIV divider is selected by programming 0x01 to 0x7E for /2 to /127, respectively, into the QDIV field of the SYSPLLCFG1 register. SYSPLLCFG1.QDIV=0x00 is an invalid configuration. The effective feedback divider can be calculated from the QDIV register setting as shown in Equation 7.
The output frequency of the VCO fVCOis given in Equation 8.
The VCO output sources three separate SYSPLL outputs (SYSPLLCLK0, SYSPLLCLK1, and SYSPLLCLK2X). Each output has its own divider unit to enable generation of up to 3 different output frequencies for use by different modules in the device. The third output (SYSPLLCLK2X) also contains a frequency doubler before the divider unit to provide a wider range of output frequencies and lower power consumption.
For SYSPLLCLK2X, the output divider can be set from /1 to /16 in steps of 1. To set the SYSPLLCLK2X output divider, program 0x0-0xF for /1 up to /16, respectively, into the RDIVCLK2X field in the SYSPLLCFG0 register. Equation 9 shows how to compute the effective SYSPLLCLK2X divider based on a given RDIVCLK2X register setting.
For SYSPLLCLK1 and SYSPLLCLK0, the output dividers can be set from /2 to /32 in steps of 2. To set the SYSPLLCLK0 or SYSPLLCLK1 output divider, program 0x0-0xF for /2 to /32, respectively, into the corresponding RDIVCLKx field in the SYSPLLCFG0 register. Equation 10 shows how to compute the effective SYSPLLCLK0 divider based on a given RDIVCLK0 setting, and Equation 11 shows how to compute the effective SYSPLLCLK1 divider based on a given RDIVCLK1 setting.
The SYSPLL output clock frequencies are thus set by the combination of fVCO and the respective dividers:
After configuration, enable the SYSPLL by setting the SYSPLLEN bit in the HSCLKEN register. Before enabling the SYSPLL, make sure that the SYSPLL is in a disabled state by verifying that the SYSPLLOFF bit in the CLKSTATUS register is set. After the SYSPLL is enabled, application software must not disable it until the SYSPLLGOOD or SYSPLLOFF bit is set in the CLKSTATUS register, indicating that the SYSPLL transitioned to a stable active state or a stable dead state. When the SYSPLL is enabled, the SYSPLL reference clock selection must not be changed.
To illustrate the above relationships, take as an example the following requirements:
To achieve this, the VCO can be configured for 80MHz through the use of PDIV and QDIV. Then, SYSPLLCLK1 can feed CANCLK with an output divider of /2, and SYSPLLCLK2X can feed MCLK with an output divider of /2.
The steps below describe how to configure the CKM to use SYSPLL in this way:
The SYSPLL divider values used in this example are summarized below for reference.
Parameter | Register | Bit Field | Bit Field Value | Actual Divider |
---|---|---|---|---|
Input reference clock divider | SYSPLLCFG1 | PDIV | 0x1 | /2 |
VCO feedback loop divider | SYSPLLCFG1 | QDIV | 0x4 | /5 |
Output clock 1 divider | SYSPLLCFG0 | RDIVCLK1 | 0x0 | /2 |
Output clock 2X divider | SYSPLLCFG0 | RDIVCLK2X | 0x1 | /2 |
In cases where there are multiple combinations of PDIV, QDIV, and RDIVCLKx that provide the desired output frequencies, consider these tuning guidelines to determine the best possible values for an application: