SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
All peripherals on a device, with the exception of infrastructure peripherals such as SYSCTL itself and the IOMUX, contain a power enable control register (PWREN) with a KEY and ENABLE field. Before any other peripheral registers are configured by software, the peripheral itself must be enabled by writing the ENABLE bit together with the appropriate KEY value to the peripheral's PWREN register.
When a peripheral ENABLE bit is cleared, the peripheral can be considered to be inactive and the remaining peripheral-specific registers are isolated from the peripheral bus and thus are not be accessible for read/write operations.