SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The SPI includes a programmable bit rate clock divider and prescaler to generate the serial output clock (SCLK).
Bit rates supported are up to, the input clocks divided by 2. The input clock selection depends on the specific device, refer to the device data sheet and Clock Control section.
The SPI functionality can work with any of these selected inputs : SYSCLK, MFCLK and LFCLK
"SPI Clock" is the output after clock division performed according to ratio selected by the CLKDIV register. SPI clock = Selected input clock / (1 + CLKDIV)
SPI Sampling Clock (SCLK) is the output after dividing the SPI Clock by the Prescalar value. SCLK = SPI Clock / ((1 + SCR )*2)
If the factor of two (*2) is set by CLKDIV the input clock must be at least 2 times faster than SPI clock.