SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
MSPM0 devices include several diagnostic mechanism to detect errors at runtime. Table 2-15 lists error sources and their corresponding handling mechanism.
Error Source | Error | Handling Mechanism |
---|---|---|
Flash (if device has ECC) | Non-correctable ECC error (if device has ECC) |
|
Correctable ECC error (if device has ECC) |
|
|
SRAM | Non-correctable ECC error (if device has ECC) |
|
Correctable ECC error (if device has ECC) |
|
|
Parity error (if device has parity) |
|
|
Address error on CPU access |
|
|
Address error on DMA access |
|
|
ECC error on CAN SRAM (if device has CAN-FD) |
|
|
SHUTDNSTOREx Memory (if present) | Parity error |
|
CKM | MCLK failure |
|
LFCLK failure (if present) |
|
|
CPUSS (if device has MPU) | Memory protection unit violation |
|
WWDT | WWDT0 violation |
|
WWDT1 violation (if present) |
|
|
PMU | Trim parity error |
|
POR0- supply error |
|
|
BOR0- supply error |
|
|
BOR1/2/3- supply error |
|
|
CPUSS | Memory protection unit violation (if present) |
|
Error sources can be configured to trigger either a nonmaskable interrupt or a different handling mechanism. The SYSTEMCFG register in SYSCTL may be used to specify the desired error handling mechanism. For example, the WWDT0 may be configured to generate either a BOOTRST or an NMI, with BOOTRST being the default case. Refer to the SYSTEMCFG register for the relevant device subfamily for the available error handling options.