SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The AES module provides four trigger sources which can be configured to source DMA trigger 1. In order of decreasing interrupt priority, the DMA1 trigger events from the AES are given in Table 31-774. When the DMA1 channel is needed by the AES for block cipher operations, the DMA1 trigger should be unmasked in the IMASK register of DMA_TRIG1 and the DMA should be configured as needed to support the AES operation.
Index (IIDX) | Name | Description |
---|---|---|
0 | AESRDY | Not to be used for normal operation. |
1 | DMA0 | Not to be used for normal operation. |
2 | DMA1 | DMA1 trigger indication |
3 | DMA2 | Not to be used for normal operation. |
The DMA trigger 1 event configuration is managed with the DMA_TRIG1 event management registers. See Section 8.2.5 for guidance on configuring the event registers for DMA triggers.