SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The default operating configuration of the device provides basic functionality which can be suitable for many applications without modification.
MSPM0Gxx devices power up and release reset for execution of application code when the external supply (VDD and VSS) reaches 1.62V. When the application code is released for execution, the device is in RUN mode with MCLK, which is sourced from the internal SYSOSC at 32 MHz. The CPUCLK and ULPCLK are also 32 MHz, derived from MCLK. LFCLK starts automatically, sourced from the internal LFOSC. In RUN mode with the default configuration, all peripherals are available to be enabled. Peripherals such as the DMA, CRC, and AES run directly from MCLK at the MCLK rate. Other peripherals, such as timers and serial interfaces, can run from the bus clock at 32 MHz or from the low-frequency 32kHz clock (LFCLK) based on their peripheral clock selection.
Power consumption can be reduced by entering SLEEP, STOP, STANDBY, or SHUTDOWN mode. By default, these modes behave in the following way: