SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
The frequency of the source clock can be computed after capture if the trigger time is known. The frequency is computed by dividing the number of source clock cycles captured by the trigger time. For example, if the trigger source was a 32.768kHz clock, the trigger mode was rising-edge to rising-edge, and the period count was 1, then the trigger time is one 32.768kHz clock period (30.5µs). If the captured source count were to come back as 122, the frequency of the source clock is computed as 122 divided by 30.5µs, giving a source clock frequency of approximately 3.99MHz.
The FCC is accuracy is dependent on the trigger clock accuracy as well as the total number of clock cycles captured. The FCC intrinsic error is ≤2 source clock cycles per capture due to synchronization of the trigger to the source clock. Therefore, the impact of these two clock cycles is reduced as more cycles are counted (as the trigger time is increased and/or the source clock frequency is increased). Approximate intrinsic error of the FCC for various source clock frequencies captured against one 32.678kHz period (FCCTRIGCNT=0) and 32 clock periods (FCCTRIGCNT=31) are given in Table 2-10.
Use Case (Source Clock Frequency) | FCC Trigger Time | FCC Count Result | FCC Count Uncertainty | Approximate FCC Intrinsic Uncertainty Error |
---|---|---|---|---|
4MHz source clock | 30.5µs | 122 | 2 cycles | 1.6% |
976.6µs | 3906 | 0.05% | ||
16MHz source clock | 30.5µs | 488 | 0.4% | |
976.6µs | 15625 | 0.01% | ||
24MHz source clock | 30.5µs | 732 | 0.27% | |
976.6µs | 23437 | 0.01% | ||
32MHz source clock | 30.5µs | 976 | 0.20% | |
976.6µs | 31250 | 0.01% | ||
80MHz source clock | 30.5µs | 2441 | 0.08% | |
976.6µs | 78125 | 0.003% |