SLAU846B June 2023 – November 2024 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3519
MSPM0G devices support basic instruction execution trace to obtain context of the sequence of execution which led to a certain state of the processor. The processor trace engine is based on the Arm CoreSight MTB-M0+ micro trace buffer.
The MTB captures the processor's program counter (PC) state when the PC changes in a nonsequential way due to a branch instruction or an exception. Load and store activity is not captured by the MTB. When nonsequential execution is detected by the MTB, the change is captured and stored into a small buffer memory (described in Table 31-2) which can be read out later by application software or the debug probe.
Start Address | End Address | Length |
---|---|---|
0x4040.3000 | 0x4040.3020 | 32B (4 trace packets) |
For each trace capture, the MTB stores the source address (the address which was branched from) and the destination address (the address which was branched to) into the buffer memory. Thus, two 32-bit words are used per trace capture packet. Because instructions are half-word aligned, the LSBs of the addresses are not required and are thus used to store additional context about the state into the trace packet.
In the case of an exception return, two trace packets are stored into the buffer memory: