SLAZ102AB October   2012  – May 2021 CC430F6137

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC24
    2. 6.2  ADC25
    3. 6.3  ADC27
    4. 6.4  ADC29
    5. 6.5  ADC42
    6. 6.6  ADC69
    7. 6.7  AES1
    8. 6.8  BSL7
    9. 6.9  COMP4
    10. 6.10 COMP10
    11. 6.11 CPU18
    12. 6.12 CPU20
    13. 6.13 CPU21
    14. 6.14 CPU22
    15. 6.15 CPU23
    16. 6.16 CPU24
    17. 6.17 CPU25
    18. 6.18 CPU26
    19. 6.19 CPU27
    20. 6.20 CPU28
    21. 6.21 CPU29
    22. 6.22 CPU30
    23. 6.23 CPU31
    24. 6.24 CPU32
    25. 6.25 CPU33
    26. 6.26 CPU34
    27. 6.27 CPU35
    28. 6.28 CPU39
    29. 6.29 CPU40
    30. 6.30 CPU46
    31. 6.31 CPU47
    32. 6.32 DMA4
    33. 6.33 DMA7
    34. 6.34 DMA8
    35. 6.35 DMA10
    36. 6.36 EEM8
    37. 6.37 EEM9
    38. 6.38 EEM11
    39. 6.39 EEM13
    40. 6.40 EEM14
    41. 6.41 EEM16
    42. 6.42 EEM17
    43. 6.43 EEM19
    44. 6.44 EEM23
    45. 6.45 FLASH29
    46. 6.46 FLASH31
    47. 6.47 FLASH37
    48. 6.48 JTAG20
    49. 6.49 JTAG26
    50. 6.50 JTAG27
    51. 6.51 LCDB1
    52. 6.52 LCDB3
    53. 6.53 LCDB4
    54. 6.54 LCDB5
    55. 6.55 LCDB6
    56. 6.56 MPY1
    57. 6.57 PMAP1
    58. 6.58 PMM8
    59. 6.59 PMM9
    60. 6.60 PMM10
    61. 6.61 PMM11
    62. 6.62 PMM12
    63. 6.63 PMM14
    64. 6.64 PMM15
    65. 6.65 PMM17
    66. 6.66 PMM18
    67. 6.67 PMM20
    68. 6.68 PORT15
    69. 6.69 PORT16
    70. 6.70 PORT17
    71. 6.71 PORT19
    72. 6.72 PORT21
    73. 6.73 RF1A1
    74. 6.74 RF1A2
    75. 6.75 RF1A3
    76. 6.76 RF1A5
    77. 6.77 RF1A6
    78. 6.78 RF1A8
    79. 6.79 RTC3
    80. 6.80 RTC6
    81. 6.81 SYS16
    82. 6.82 TAB23
    83. 6.83 UCS6
    84. 6.84 UCS7
    85. 6.85 UCS9
    86. 6.86 UCS10
    87. 6.87 UCS11
    88. 6.88 USCI26
    89. 6.89 USCI30
    90. 6.90 USCI31
    91. 6.91 USCI34
    92. 6.92 USCI35
    93. 6.93 USCI39
    94. 6.94 USCI40
    95. 6.95 WDG4
  7. 7Revision History

6.18 CPU26

CPU Module

Category

Compiler-Fixed

Function

CALL SP instruction does not behave as expected

Description

The intention of the CALL SP instruction is to execute code from the stack, instead it skips the first piece of data (instruction) on the stack. The second piece of data at SP+2 is used as the first executable instruction.

Workaround

Write the op code for a NOP as the first instruction on the stack. Begin the intended subroutine at address SP + 2.

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes
IAR Embedded Workbench Not affected
TI MSP430 Compiler Tools (Code Composer Studio) v4.1.3 or later
MSP430 GNU Compiler (MSP430-GCC) Not affected