SLAZ160J October 2012 – May 2021 MSP430F2121
CPU Module
Functional
CPU speed performance limitation
The CPU register contents may become unpredictable during CPU register operations if the device operates at minimum Vcc required for system speed performance above 6MHz when using LFXT1 in HF mode (BCSCTL1.XTS = 1) and sourcing MCLK to clock the CPU under certain conditions. This is dependent on voltage and CPU clock (MCLK) frequency and duty-cycle.
With respect to the system speed performance above 6MHz versus minimum required Vcc
1. Use external clocks with 50% positive duty cycle when sourced to MCLK
OR
2. Use internally divided clock for MCLK (BCSCTL2.DIVMx > 00)
OR
3. Reduce LFXT1 (used in HF mode) or external clock frequency by 20% when sourced to MCLK