SLAZ165O October 2012 – May 2021 MSP430F2234
CPU Module
Functional
CPU speed performance limitation
The CPU register contents may become unpredictable during CPU register operations if the device operates at minimum Vcc required for system speed performance above 4.15MHz under certain conditions. This is dependent on voltage and CPU clock (MCLK) frequency and duty-cycle.
With respect to the system speed performance above 4.15MHz versus minimum required Vcc
1. Increase Vcc by 200mV for DCO calibrated frequencies when sourced to MCLK
OR
2. Use internally divided clock for MCLK (BCSCTL2.DIVMx > 00)
OR
3. Use external clock with 50% positive duty cycle when sourced to MCLK
OR
4. Reduce LFXT1 (used in HF mode) or external clock frequency by 20% when sourced to MCLK
OR
5. Reduce DCO speed by 20% when DCO is sourced to MCLK