SLAZ167O October   2012  – May 2021 MSP430F2254

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DA38
      2.      RHA40
      3.      YFF49
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL12
    2. 6.2  BCL13
    3. 6.3  BCL16
    4. 6.4  CPU14
    5. 6.5  CPU19
    6. 6.6  CPU45
    7. 6.7  EEM20
    8. 6.8  FLASH21
    9. 6.9  FLASH22
    10. 6.10 FLASH24
    11. 6.11 FLASH26
    12. 6.12 FLASH27
    13. 6.13 FLASH36
    14. 6.14 JTAG13
    15. 6.15 JTAG14
    16. 6.16 PORT10
    17. 6.17 SYS15
    18. 6.18 TA12
    19. 6.19 TA16
    20. 6.20 TA21
    21. 6.21 TAB22
    22. 6.22 TB2
    23. 6.23 TB16
    24. 6.24 TB24
    25. 6.25 USCI16
    26. 6.26 USCI20
    27. 6.27 USCI21
    28. 6.28 USCI22
    29. 6.29 USCI23
    30. 6.30 USCI24
    31. 6.31 USCI25
    32. 6.32 USCI26
    33. 6.33 USCI27
    34. 6.34 USCI30
    35. 6.35 USCI34
    36. 6.36 USCI35
    37. 6.37 USCI40
    38. 6.38 XOSC5
    39. 6.39 XOSC8
  7. 7Revision History

6.4 CPU14

CPU Module

Category

Functional

Function

Erroneous setting of SCG0 after reset

Description

The SCG0 bit in the CPU status register (SR) is set after any reset (PUC or POR) if bit #6 in the reset vector destination address is set. Setting SCG0 turns off the DCO dc generator when DCOCLK is not used for MCLK or SMCLK.

Workaround

1) As the error only occurs after PUC or POR, it is sufficient to clear the SCG0 bit at the beginning of the program code; for example:
bic.w #SCG0, SR

OR

2) Avoid using reset destination addresses where bit #6 is set. Allowed reset vector destination addresses are: xx0xh, xx1xh, xx2xh, xx3xh, xx8xh, xx9xh, xxAxh, xxBxh.