SLAZ281AA October 2012 – May 2021 MSP430F5419
EEM Module
Debug
No breakpoint stop reaction at DMA/CPU switch
If an address-related trigger, such as the general IDE breakpoint, is triggered for a CPU instruction one cycle after a DMA transaction, the stop reaction will not be accepted by the EEM (will not halt program execution). A data related trigger set at a DMA transaction one cycle after a CPU instruction results in the same behavior.
Use trigger configurations that are not dependent on DMA/not-DMA transactions (Read, Write, or Don't Care). The State Storage Block can then be used at program stop to determine:
- Whether the trigger-causing event was a DMA or a non-DMA transaction
- The state of the program at the time of the event