SLAZ281AA October 2012 – May 2021 MSP430F5419
SYS Module
Functional
Sporadic device crash on LPMx
If an interrupt occurs within 5 ns of the last rising edge of the MCLK prior to entering low-power mode (LPMx), the flash controller experiences a glitch that latches the last address on the address bus. This is the address that contains the opcode following the entry to LPMx.
When the core then requests the address for the interrupt handler routine, the flash instead returns the the data at the address that was latched. This data is interpreted as the address for the interrupt handler, resulting in errant code execution and an eventual reset condition.
None.