SLAZ441K March   2013  – May 2021 MSP430G2955

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DA38
      2.      RHA40
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL12
    2. 6.2  CPU4
    3. 6.3  SYS15
    4. 6.4  TA12
    5. 6.5  TA16
    6. 6.6  TA21
    7. 6.7  TAB22
    8. 6.8  TAB26
    9. 6.9  TAB26
    10. 6.10 TB2
    11. 6.11 TB16
    12. 6.12 TB24
    13. 6.13 USCI20
    14. 6.14 USCI22
    15. 6.15 USCI23
    16. 6.16 USCI24
    17. 6.17 USCI25
    18. 6.18 USCI26
    19. 6.19 USCI29
    20. 6.20 USCI30
    21. 6.21 USCI34
    22. 6.22 USCI35
    23. 6.23 USCI40
    24. 6.24 XOSC5
  7. 7Revision History

6.13 USCI20

USCI Module

Category

Functional

Function

I2C Mode Multi-master transmitter issue

Description

When configured for I2C master-transmitter mode, and used in a multi-master environment, the USCI module can cause unpredictable bus behavior if all of the following four conditions are true:

1 - Two masters are generating SCL
And
2 - The slave is stretching the SCL low phase of an ACK period while outputting NACK on SDA
And
3 - The slave drives ACK on SDA after the USCI has already released SCL, and then the SCL bus line gets released
And
4 - The transmit buffer has not been loaded before the other master continues communication by driving SCL low

The USCI will remain in the SCL high phase until the transmit buffer is written. After the transmit buffer has been written, the USCI will interfere with the current bus activity and may cause unpredictable bus behavior.

Workaround

1 - Ensure that slave doesn't stretch the SCL low phase of an ACK period
Or
2 - Ensure that the transmit buffer is loaded in time
Or
3 - Do not use the multi-master transmitter mode