SLAZ471Z May   2014  – August 2021 MSP430FR5967

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
    3.     9
  6.   10
    1.     11
    2.     12
    3.     13
    4.     14
    5.     15
    6.     16
    7.     17
    8.     18
    9.     19
    10.     20
    11.     21
    12.     22
    13.     23
    14.     24
    15.     25
    16.     26
    17.     27
    18.     28
    19.     29
    20.     30
    21.     31
    22.     32
    23.     33
    24.     34
    25.     35
    26.     36
    27.     37
    28.     38
    29.     39
    30.     40
    31.     41
    32.     42
    33.     43
    34.     44
    35.     45
    36.     46
    37.     47
    38.     48
    39.     49
    40.     50
    41.     51
    42.     52
    43.     53
    44.     54
    45.     55
    46.     56
    47.     57
  7.   58

6.27 EEM28

EEM Module

Category

Debug

Function

Clock outputs observed on port module during LPMx in debug mode

Description

When the device is in LPMx mode, if a debug halt is requested and if the port pin is configured as MCLK, SMCLK, or ACLK output, these clocks are observed on the port pin. Depending on the LPM mode (see Device User's Guide), peripherals that are clocked from MCLK, SMCLK, or ACLK are still halted during debug halt state.

For example, if the device is in debug halt in LPM3 mode and a port pin is configured as SMCLK output, SMCLK can be observed on the pin. But the peripherals sourced from SMCLK are still halted as expected.

Workaround

None