SLAZ517AG March   2013  – August 2021 MSP430FR6989

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
    3.     10
  6.   11
    1.     12
    2.     13
    3.     14
    4.     15
    5.     16
    6.     17
    7.     18
    8.     19
    9.     20
    10.     21
    11.     22
    12.     23
    13.     24
    14.     25
    15.     26
    16.     27
    17.     28
    18.     29
    19.     30
    20.     31
    21.     32
    22.     33
    23.     34
    24.     35
    25.     36
    26.     37
    27.     38
    28.     39
    29.     40
    30.     41
    31.     42
    32.     43
    33.     44
    34.     45
    35.     46
    36.     47
    37.     48
    38.     49
    39.     50
    40.     51
    41.     52
    42.     53
    43.     54
    44.     55
    45.     56
    46.     57
    47.     58
  7.   59

6.36 PMM32

PMM Module

Category

Functional

Function

Device may enter lockup state or execute unintentional code during transition from AM to LPM2/3/4

Description

The device might enter lockup state or start executing unintentional code  resulting in unpredictable behavior depending on the contents of the address location- if any of the two conditions below occurs:

Condition1:

The following three events happen at the same time:

1) The device transitions from AM to LPM2/3/4 (e.g. during ISR exits or Status Register modifications),

AND

2) An interrupt is requested (e.g. GPIO interrupt),

AND

3)  MODCLK is requested (e.g. triggered by ADC) or removed (e.g. end of ADC conversion).

Modules which can trigger MODCLK clock requests/removals are ADC and eUSCI.

If clock events are started by the CPU (e.g. eUSCI during SPI master transmission), they can not occur at the same time as the power mode transition and thus should not be affected. The device should only be affected when the clock event is asynchronous to the power mode transition.

The device can recover from this lockup condition by a PUC/BOR/Power cycle (e.g. enable Watchdog to trigger PUC).

Condition2:

The following events happen at the same time:

1) The device transitions from AM to LPM2/3/4 (e.g. during ISR exits or Status Register modifications),

AND

2) An interrupt is requested (e.g. GPIO interrupt),

AND

3) Neither MODCLK nor SMCLK are running (e.g. requested by a peripheral),

AND

4)  SMCLK is configured with a different frequency than MCLK.

The device can recover from this lockup condition by a BOR/Power cycle.

Workaround

1. Use LPM0/1/x.5 instead of LPM2/3/4.

OR

2. Place the FRAM in INACTIVE mode before any entry to LPM2/3/4 by clearing the FRPWR bit and FRLPMPWR bit (if exist) in the GCCTL0 register. This must be performed from RAM as shown below:

// define a function in RAM
#pragma CODE_SECTION(enterLpModeFromRAM,".TI.ramfunc")
void enterLpModeFromRAM(unsigned short lowPowerMode);

//call this function before any entry to LPM2/3/4
void enterLpModeFromRAM(unsigned short lowPowerMode)
{
FRCTL0 = FRCTLPW;
GCCTL0 &= ~(FRPWR+FRLPMPWR); //clear FRPWR and FRLPMPWR
FRCTL0_H = 0; //re-lock FRCTL
__bis_SR_register(lowPowerMode);
}