SLAZ660S June   2015  – May 2021 MSP430FR2633

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RHB32
      2.      YQW24
      3.      DA32
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC50
    2. 6.2  ADC63
    3. 6.3  BSL18
    4. 6.4  CPU21
    5. 6.5  CPU22
    6. 6.6  CPU40
    7. 6.7  CPU46
    8. 6.8  CS13
    9. 6.9  EEM23
    10. 6.10 GC4
    11. 6.11 GC5
    12. 6.12 PMM32
    13. 6.13 PORT28
    14. 6.14 RTC15
    15. 6.15 USCI42
    16. 6.16 USCI45
    17. 6.17 USCI47
    18. 6.18 USCI50
  7. 7Revision History

6.16 USCI45

USCI Module

Category

Functional

Function

Unexpected SPI clock stretching possible when UCxCLK is asynchronous to MCLK

Description

In rare cases, during SPI communication, the clock high phase of the first data bit may be stretched significantly. The SPI operation completes as expected with no data loss. This issue only occurs when the USCI SPI module clock (UCxCLK) is asynchronous to the system clock (MCLK).

Workaround

Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are synchronous to each other.