Advisories that affect the device's operation, function, or parametrics.
✓ The check mark indicates that the issue is present in the specified revision.
Advisories that affect factory-programmed software.
✓ The check mark indicates that the issue is present in the specified revision.
Errata Number | Rev A |
---|---|
BSL14 | ✓ |
Advisories that are resolved by compiler workaround. Refer to each advisory for the IDE and compiler versions with a workaround.
✓ The check mark indicates that the issue is present in the specified revision.
Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds.
TI MSP430 Compiler Tools (Code Composer Studio IDE)
MSP430 GNU Compiler (MSP430-GCC)
IAR Embedded Workbench
The revision of the device can be identified by the revision letter on the Package Markings or by the HW_ID located inside the TLV structure of the device.
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
Support tool naming prefixes:
X: Development-support product that has not yet completed Texas Instruments internal qualification testing.
null: Fully-qualified development-support product.
XMS devices and X development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format.
BGA (ZQW), 113 Pin
LQFP (PZ) 100 Pin
NFBGA (ZCA), 113 Pin
Die Revision | TLV Hardware Revision |
---|---|
Rev A | 10h |
Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User's Guide.
BSL Module
Software in ROM
BSL request to unlock the JTAG
The feature in the BSL to keep the JTAG unlocked by setting the bit BSL_REQ_JTAG_OPEN in the return value has been disabled in this device.
None
COMP Module
Functional
Comparator port output toggles when entering or leaving LPM3/LPM4
The comparator port pin output (CECTL1.CEOUT) erroneously toggles when device enters or leaves LPM3/LPM4 modes under the following conditions:
1) Comparator is disabled (CECTL1.CEON = 0)
AND
2) Output polarity is enabled (CECTL1.CEOUTPOL = 1)
AND
3) The port pin is configured to have CEOUT functionality.
For example, if the CEOUT pin is high when the device is in Active Mode, CEOUT pin becomes low when the device enters LPM3/LPM4 modes.
When the comparator is disabled, ensure at least one of the following:
1) Output inversion is disabled (CECTL.CEOUTPOL = 0)
OR
2) Change pin configuration from CEOUT to GPIO with output low.
CPU Module
Compiler-Fixed
Using POPM instruction on Status register may result in device hang up
When an active interrupt service request is pending and the POPM instruction is used to set the Status Register (SR) and initiate entry into a low power mode , the device may hang up.
None. It is recommended not to use POPM instruction on the Status Register.
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | Not affected | |
TI MSP430 Compiler Tools (Code Composer Studio) | v4.0.x or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU21 |
MSP430 GNU Compiler (MSP430-GCC) | MSP430-GCC 4.9 build 167 or later |
CPU Module
Compiler-Fixed
Indirect addressing mode with the Program Counter as the source register may produce unexpected results
When using the indirect addressing mode in an instruction with the Program Counter (PC) as the source operand, the instruction that follows immediately does not get executed.
For example in the code below, the ADD instruction does not get executed.
mov @PC, R7
add #1h, R4
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | Not affected | |
TI MSP430 Compiler Tools (Code Composer Studio) | v4.0.x or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU22 |
MSP430 GNU Compiler (MSP430-GCC) | MSP430-GCC 4.9 build 167 or later |
CPU Module
Functional
Wrong program trace display in the debugger while using conditional jump instructions
The state storage window displays an incorrect sequence of instructions when:
1. Conditional jump instructions are used to form a software loop
AND
2. A false condition on the jump breaks out of the loop
In such cases the trace buffer incorrectly displays the first instruction of the loop as the instruction that is executed immediately after exiting the loop.
Example:
Actual Code:
mov #4,R4
LABEL mov #1,R5
dec R4
jnz LABEL
mov #2,R6
nop
State Storage Window Displays:
LABEL mov #1,R5
dec R4
jnz LABEL
mov #1,R5
nop
None
Note: This erratum affects the trace buffer display only. It does not affect code execution in debugger or free run mode
CPU Module
Compiler-Fixed
PC is corrupted when executing jump/conditional jump instruction that is followed by instruction with PC as destination register or a data section
If the value at the memory location immediately following a jump/conditional jump instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination register or a data section (const data in flash memory or data variable in
RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed; therefore, branching to a wrong address location in code and leading to wrong program execution.
For example, a conditional jump instruction followed by data section (0140h).
@0x8012 Loop DEC.W R6
@0x8014 DEC.W R7
@0x8016 JNZ Loop
@0x8018 Value1 DW 0140h
In assembly, insert a NOP between the jump/conditional jump instruction and program code with instruction that contains PC as destination register or the data section.
Refer to the table below for compiler-specific fix implementation information.
IDE/Compiler | Version Number | Notes |
---|---|---|
IAR Embedded Workbench | IAR EW430 v5.51 or later | For the command line version add the following information Compiler: --hw_workaround=CPU40 Assembler:-v1 |
TI MSP430 Compiler Tools (Code Composer Studio) | v4.0.x or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU40 |
MSP430 GNU Compiler (MSP430-GCC) | Not affected |
CPU Module
Functional
An unexpected Vacant Memory Access Flag (VMAIFG) can be triggered
An unexpected Vacant Memory Access Flag (VMAIFG) can be triggered, if a PC-modifying instruction (e.g. - ret, push, call, pop, jmp, br) is fetched from the last addresses (last 4 or 8 byte) of a memory (e.g.- FLASH, RAM, FRAM) that is not contiguous to a higher, valid section on the memory map.
In debug mode using breakpoints the last 8 bytes are affected.
In free running mode the last 4 bytes are affected.
Edit the linker command file to make the last 4 or 8 bytes of affected memory sections unavailable, to avoid PC-modifying instructions on these locations.
Remaining instructions or data can still be stored on these locations.
CTSD Module
Functional
CTSD16OFFG bit erroneously set while CTSD16 module is inactive
The CTSD16CTL.CTSD16OFFG bit is erroneously set when the CTSD16 module is disabled and not actively converting (CTSD16CCTLx.CTSD16SC = 0). This CTSD16CTL.CTSD16OFFG bit can only be cleared once the CTSD16 module is enabled and actively converting (CTSD16CCTLx.CTSD16SC = 1).
This errata effectively nullifies the ability to trigger NMI interrupts in response to oscillator faults, unless CTSD16 is kept enabled.
1) If CTSD16 is enabled, and the fault condition is ensured not to be present, then CTSD16OFFG and OFIFG can function normally. The only way to keep CTSD16 enabled indefinitely is by setting CTSD16SC.
2) While CTSD16 is not enabled, the OFIFG bit cannot be used. The other bits sourcing into it besides CTSD16OFFG (that is, XT1LFOFFG, XT1HFOFFG, XT2OFFG, and DCOFFG) can be polled or checked by software individually; but the ability to trigger the NMI upon OFIFG becoming set is no longer possible.