SLAZ681O September   2015  – August 2021 MSP430FR5994

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
      3.      10
      4.      11
    3.     12
  6.   13
    1.     14
    2.     15
    3.     16
    4.     17
    5.     18
    6.     19
    7.     20
    8.     21
    9.     22
    10.     23
    11.     24
    12.     25
    13.     26
    14.     27
    15.     28
    16.     29
    17.     30
    18.     31
    19.     32
    20.     33
  7.   34

6.18 USCI45

USCI Module

Category

Functional

Function

Unexpected SPI clock stretching possible when UCxCLK is asynchronous to MCLK

Description

In rare cases, during SPI communication, the clock high phase of the first data bit may be stretched significantly. The SPI operation completes as expected with no data loss. This issue only occurs when the USCI SPI module clock (UCxCLK) is asynchronous to the system clock (MCLK).

Workaround

Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are synchronous to each other.