SLDA021B March   2014  – February 2020 AM3892 , AM3894

 

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2.2.2.1 PCB Layer Count for Standard BGA Arrays

The layers required to route a particular design can be easily estimated given the number and locations of signals. Assuming the PCB feature sizes in Table 2, the PCB would be routed as follows:

  • The first 2 rows will route on the top layer. The second 2 rows will route on the second layer. An additional PCB layer will be required for every row in past the first 2.
  • Therefore, if "Rows_in" = the maximum number of rows in (from the outside of the BGA array) the centermost signal is located, then:
    • 2 Rows_in = 1 PCB signal layer
    • 3 Rows_in = 2 PCB signal layers
    • 4 Rows_in = 2 PCB signal layers
    • 5 Rows_in = 3 PCB signal layers
    • 6 Rows_in = 4 PCB signal layers
    • 7 Rows_in = 5 PCB signal layers

For example, if a signal called I2C_CLK were required in the design, and it was located five rows in from the outside (counting all rows), then it would require 3 PCB signal layers, plus at least 2 PCB layers for power and ground, adding to 5 layers total. Because PCBs are manufactured with layer symmetry about the centerline, a 6 layer PCB would be specified.

Depending on the power requirements and the power signal routing, an additional power layer may be required, but can be avoided with strategic design practices.