SLLA612 august   2023 TMDS1204

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2General Configuration Pin
  6. 3Transmitter Configuration
  7. 4Receiver Configuration
  8.   References

2 General Configuration Pin

EN: When low, TMDS1204 will be held in reset. The EN pin has a internal 250k pull-up to VIO. For passive circuitry implementation, it is recommended to add an external 0.22 µF pull-down capacitor on the EN pin.

VIO: The TMDS1204 supports 1.2-V, 1.8-V, and 3.3-V LVCMOS levels depending on the source I/O voltage requirement. The VIO pin is used to select which voltage level is used for the following 2-level control pins: LV_DDC_SDA, LV_DDC_SCL, SCL/CFG0, and SDA/CFG1.

Table 2-1 VIO Voltage Based on the LVCMOS Signaling Level
VIO Pin LVCMOS Signaling Level
VIO < 1.5 V 1.2 V
1.5 V < VIO < 2.5 V 1.8 V
VIO > 2.5 V 3.3 V

Mode (pin-strap or I2C mode): The MODE pin provides four modes of operation: three pin-strap modes and one I2C mode.

In all three pin strap modes, the DDC snooping feature is enabled. In I2C mode, the DDC snoop feature is enabled by default but can be disabled by a register.

Table 2-2 Mode Pin Setting
Mode Description
0 Pin-strap mode with fixed receiver equalizer
R Pin-strap mode with flexible receiver equalizer and fan-out buffer support
F I2C mode
1 Pin-strap mode with flexible receiver equalizer with no fan-out buffer support
Fan-out buffer: In some applications a HDMI sink requires the clock and data must be on separate paths. The TMDS1204 implements a fan-out buffer feature to support such applications. When the fan-out buffer feature is enabled, the TMDS1204 will output the HDMI clock on RCLKOUTp/n when operating in HDMI 1.4 or HDMI 2.0. The OUT_CLKp/n will be disabled. When operating in HDMI 2.1 FRL mode, the TMDS1204 will output FRL data lane 3 on OUT_CLKp/n. RCLKOUTp/n will be disabled. The feature is enabled in pin-strap mode when MODE pin = "R" or it can be enabled through FANOUT_EN register when TMDS1204 is configured for I2C mode. However, the fan-out buffer feature will be disabled if swap is enabled.

SCL/CFG0: In pin-strap mode, this is the CFG0 pin. It is recommended to tie this pin to '0' for normal HDMI mode. In I2C mode, this is the SCL pin.

SDA/CFG1: In pin-strap mode, this is the CFG1 pin. The CFG1 pin needs to be set to '0' for normal lane ordering, but set to '1' if the input/output lane order is swapped. In I2C mode, this is the SDA pin.

LINEAR_EN pin: The TMDS1204 supports both linear and limited modes and it's recommended to operate in each mode for sink and source applications, respectively. When configured as a linear redriver, the TMDS1204 differential output levels are a linear function of the GPU output levels enabling TMDS1204 to be transparent to link training and operate as a channel shortener. When configured as a limited redriver, the TMDS1204 differential output voltage levels are independent of the graphics process unit (GPU) output levels ensuring HDMI compliant levels at the receptacle.

The TMDS1204 in pin-strap mode provides the option to dynamically switch between limited and linear based on the HDMI mode of operation. It is recommended to set the LINEAR_EN pin = "F" when using this device in sink applications. It is recommended to set the LINEAR_EN pin = "0" when using this device in source applications. If using I2C mode, the LINEAR_EN register can be set to "1" to enable linear mode.

LINEAR_EN Pin Level HDMI 1.4, 2.0, or DP HDMI 2.1 FRL
0 Limited Enabled Limited Enabled
R Reserved Reserved
F Linear Enabled Linear Enabled
1 Limited Enabled Linear Enabled
Note: For HDMI2.1 in linear mode, the GPU transmitter must meet the following requirements.
GPU TX Transmitter Min Max Units
Single-ended SWING 400 500 mV
Rise/Fall time for 3, 6, 8, 10, 12Gbps FRL 16 mV/ps
SIGDET_OUT: The TMDS1204 is fully functional when a signal is detected. If no signal is detected then the device enters standby state waiting for a signal. This pin supports the input signal detect function as part of the TMDS1204 power management feature. While in standby state and the HPD_IN pin is asserted high, the TMDS1204 will assert the SIGDET_OUT pin low when the signal is detected on either IN_CLK or IN_D2 per Table 2-3. Otherwise SIGDET_OUT pin is de-asserted when entering power down or standby state. If used, the SIGDET_OUT pin requires an external pull-up resistor of 10-kΩ or greater
Table 2-3 SIGDET_OUT Signal Reference
HDMI 1.4 or 2.0 HDMI 2.1
Swap Enabled IN_D2 signal reference IN_CLK signal reference
Swap Disabled IN_CLK signal reference IN_D2 signal reference

External DDC Level Shifter: Since there is no DDC buffer function for the TMDS1204 device, an external DDC level shifter must be implemented if DDC buffering is desired. When designing with a external DDC level shifter, keep in mind that the HDMI specification limits the DDC bus capacitance to ≤ 50-pF for both an HDMI source and sink. Therefore, care must be taken to make sure that the capacitance of the external DDC level shifter does not cause the total capacitance between source or sink and the HDMI receptacle to become greater than 50-pF.