SLLSE75B May   2011  – July 2016 TLK10002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  10-Gbps Power Characteristics - 1.0 V
    6. 7.6  10-Gbps Power Characteristics - 1.5 V
    7. 7.7  10-Gbps Power Characteristics - 1.8 V
    8. 7.8  Transmitter and Receiver Characteristics
    9. 7.9  MDIO Timing Requirements
    10. 7.10 JTAG Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Speed Side Receiver Jitter Tolerance
      2. 8.3.2  Lane Alignment Scheme
      3. 8.3.3  Lane Alignment Components
      4. 8.3.4  Lane Alignment Operation
      5. 8.3.5  Channel Synchronization
      6. 8.3.6  Line Rate, SERDES PLL Settings, and Reference Clock Selection
      7. 8.3.7  Clocking Architecture
      8. 8.3.8  Loopback Modes
      9. 8.3.9  Deep Remote Loopback
      10. 8.3.10 Shallow Remote Loopback and Serial Retime
      11. 8.3.11 Deep Local Loopback
      12. 8.3.12 Shallow Local Loopback
      13. 8.3.13 Test Pattern Generation and Verification
      14. 8.3.14 Latency Measurement Function
      15. 8.3.15 Power-Down Mode
      16. 8.3.16 High Speed CML Output
      17. 8.3.17 High Speed Receiver
      18. 8.3.18 Loss of Signal Indication (LOS)
      19. 8.3.19 MDIO Management Interface
      20. 8.3.20 MDIO Protocol Timing
      21. 8.3.21 Clause 22 Indirect Addressing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Transmit (Low Speed to High Speed) Data Path
      2. 8.4.2 Receive (High Speed to Low Speed) Data Path
      3. 8.4.3 1:1 Retime Mode
    5. 8.5 Programming
      1. 8.5.1 Power Sequencing Guidelines
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Initialization Setup
      1. 9.3.1 4:1 Mode (9.8304 Gbps on HS Side, 2.4576 Gbps Per Lane on LS Side)
      2. 9.3.2 2:1 Mode (9.8304 Gbps on HS Side, 4.9152 Gbps Per Lane on LS Side, Only Lanes 0 and 1 on LS Side Active)
      3. 9.3.3 1:1 Mode (4.9152 Gbps on HS Side, 4.9152Gbps on LS side, Only Lane 0 on LS Side Active)
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 AC Coupling
      2. 11.1.2 TLK10002 Clocks: REFCLK, CLKOUT - General Information
      3. 11.1.3 External Clock Connections
      4. 11.1.4 TLK10002 Control Pins and Interfaces
        1. 11.1.4.1 MDIO Interface
        2. 11.1.4.2 JTAG Interface
        3. 11.1.4.3 Unused Pins
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

10 Power Supply Recommendations

The TLK10002 allows either the core or I/O power supply to be powered up for an indefinite period of time while the other supply is not powered up, if all of the following conditions are met:

  1. All maximum ratings and recommending operating conditions are followed.
  2. Bus contention while 1.5-V or 1.8-V power is applied ( > 0 V) must be limited to 100 hours over the projected lifetime of the device.
  3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the absolute maximum voltage values for up to 100 hours of lifetime operation at a TJ of 105°C or lower will minimally impact reliability.

The TLK10002 LVCMOS I/O are not failsafe (that is, cannot be driven with the I/O power disabled). TLK10002 inputs must not be driven high until their associated power supply is active.