SLLSEJ2G July   2015  – March 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DP159 Mother Board Application Structure
      2.      DP159 Dongle Application Structure
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9.5.1 DP-HDMI Adaptor ID Buffer

The SNx5DP159 device includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by the VESA DisplayPort Dual-Mode Standard Version 1.1, accessible by standard I2C[4] protocols through the DDC interface when the HDMI_SEL/A1 pin is low. The DP-HDMI adapter buffer and extended DDC register for Type 2 capability is accessed at target addresses 80h (Write) and 81h (Read).

The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII characters, as shown in Table 3, and supports the WRITE command procedures (accessed at target address 80h) to select the subaddress, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist Version 1.0 section 2.3.

Table 3. SNx5DP159 DP-HDMI Adaptor ID Buffer and Extended DDC

Address Description Value HDMI Value DVI Read or Read/Write
00h HDMI ID code 44h 00h Read only
01h 50h 00h
02h 2Dh 00h
03h 48h 00h
04h 44h 00h
05h 4Dh 00h
06h 49h 00h
07h 20h 00h
08h 41h 00h
09h 44h 00h
0Ah 41h 00h
0Bh 50h 00h
0Ch 54h 00h
0Dh 4Fh 00h
0Eh 52h 00h
0Fh 04h 00h
10h Video Adaptor Identifier
Bit 2:0 ADAPTOR_REVISION		 0 0 Read only
Bit 3 Reserved: but 0 for type 2 0 0
Bits 7:4 1010 = Dual mode defined by dual mode[1] standard 1010 0
11h IEE_OUI first two hex digits 08h 08h Read only
12h IEE_OUI second two hex digits 00h 00h Read only
13h IEE_OUI third two hex digits 28h 28h Read only
14h Device ID 44h 44h Read only
15h 50h 50h
16h 31h 31h
17h 35h 35h
18h 39h 39h
19h 00h 00h
1Ah Hardware revision 02h 02h Read only
Bits 7:4 major revision 00h 00h
Bits 3:0 minor revision 02h 02h
1Bh Firmware or software major revision 00h 00h Read only
1Ch Firmware or software minor revision 00h 00h Read only
1Dh Max TMDS clock rate
Default value is F0h in HDMI column
Note: Value determined by taking clock rate and dividing by 2.5 and converting to HEX. For HDMI2.0 extend as if the clock rate extended instead of its actual method, clock 1/10 DR and not 1/40 DR.		 F0h 42h Read only
1Eh If I2C_DR_CTL = 0 the value is 0Fh → If DDC_AUX_DR_SEL = 0 the value is 0Fh
If I2C_DR_CTL = 1 the value is 1Fh → If DDC_AUX_DR_SEL = 1 then value is 1Fh
If I2C_DR_CTL = 0 the value is 0Fh
If I2C_DR_CTL = 1 the value is 1Fh		 0Fh 0Fh  Read only
1Fh Reserved 00h  00h  Write/Read
20h TMDS_OE
Bit 0: 0 = TMDS_ENABLED (default)
Bit 0: 1 = TMDS_DISABLED
Bits 7:1 Reserved		 00h  00h Write/Read
21h HDMI Pin Control
Bit 0 = CEC_EN
Enables connection between the HDMI CEC pin connected to the sink and the
CONFIG2 pin to the upstream device + 27-kΩ pullup.
0 = CEC_ DISABLED (default)
1 = CEC_ ENABLED
Bits 7:1 = RESERVED		  00h 00h   Write/Read
22h Writing a bit pattern to this register that is not defined above may result in an unpredictable I2C speed selection, but the adaptor must continue to otherwise work normally. Only applicable when using I2C-over-AUX transport
01h = 1-Kbps
02h = 5-Kbps
04h = 10-Kbps
08h = 100-kbps
10h = 400-Kbps (RSVD in Dual Mode STND)
On read, the dual-mode cable adaptor returns a value to indicate the speed currently in use. The default I2C speed prior to software writing to this register is 100-Kbps.
Illegal write value shall write register default (08h). This register sets the DDC output DR whether I2C-over-AUX or straight DDC 		 08h 08h  Write/Read
23h-FFh Reserved 00h 00h Read