SLLSEK3E July   2015  – September 2017 TUSB4041I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Byte N Register
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 Downstream Port 3 Implementation
        5. 9.2.2.5 Downstream Port 4 Implementation
        6. 9.2.2.6 VBUS Power Switch Implementation
        7. 9.2.2.7 Clock, Reset, and Miscellaneous
        8. 9.2.2.8 TUSB4041I Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB4041I Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

PAP Package
64-Pin HTQFP With PowerPAD™
Top View
TUSB4041I TUSB4041I-Q1_PAP_SLLSEK4.gif
NC = No internal connection

Pin Functions

PIN I/O(1) TYPE(1) DESCRIPTION
NAME NO.
CLOCK AND RESET SIGNALS
GRSTz 18 I PU Global power reset. This reset brings all of the TUSB4041I device internal registers to the default state. When the GRSTz pin is asserted, the device is completely nonfunctional.
XI 30 I — Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal, a 1-MΩ feedback resistor is required between the XI and XO pins.
XO 29 O — Crystal output. This pin is the crystal output for the internal oscillator. If the XI pin is driven by an external oscillator, this pin may be left unconnected. When using a crystal, a 1-MΩ feedback resistor is required between the XI and XO pins.
USB UPSTREAM SIGNALS
USB_DM_UP 22 I/O — USB high-speed differential transceiver (negative)
USB_DP_UP 21 I/O — USB high-speed differential transceiver (positive)
USB_R1 32 I — Precision resistor reference. Connect a 9.53-kΩ ±1% resistor between the USB_R1 pin and ground.
USB_VBUS 16 I — USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-kΩ ±1% resistor and to ground through a 10-kΩ ±1% resistor from the signal to ground.
USB DOWNSTREAM SIGNALS
OVERCUR1z 14 I PU USB port 1 overcurrent detection. This pin is used to connect the overcurrent output of the downstream port power switch for port 1.
0 = An overcurrent event occurred.
1 = An overcurrent event has not occurred.
This pin can be left unconnected if power management is not implemented. If power management is enabled, the necessary external circuitry should be determined by the power switch.
OVERCUR2z 15 I PU USB port 2 overcurrent detection. This pin is used to connect the overcurrent output of the downstream port power switch for port 2.
0 = An overcurrent event occurred.
1 = An overcurrent event has not occurred.
If power management is not implemented, leave this pin unconnected. If power management is enabled, the necessary external circuitry should be determined by the power switch.
OVERCUR3z 12 I PU USB port 3 overcurrent detection. This pin is used to connect the overcurrent output of the downstream port power switch for port 3.
0 = An overcurrent event occurred.
1 = An overcurrent event has not occurred.
This pin can be left unconnected if power management is not implemented. If power management is enabled, the necessary external circuitry should be determined by the power switch.
OVERCUR4z 11 I PU USB port 4 overcurrent detection. This pin is used to connect the overcurrent output of the downstream port power switch for port 4.
0 = An overcurrent event occurred.
1 = An overcurrent event has not occurred.
This pin can be left unconnected if power management is not implemented. If power management is enabled, the necessary external circuitry should be determined by the power switch.
PWRCTL1/BATEN1 4 I/O PD USB port 1 power-on control for downstream power and battery charging enable. The pin is used for control of the downstream power switch for port 1.
The value of the pin is sampled at the deassertion of reset to determine the value of the battery charging support for port 1 as indicated in the Battery Charging Support Register:
0 = Battery charging not supported
1 = Battery charging supported
PWRCTL2/BATEN2 3 I/O PD USB port 2 power-on control for downstream power and battery charging enable. The pin is used for control of the downstream power switch for port 2.
The value of the pin is sampled at the deassertion of reset to determine the value of the battery charging support for Port 2 as indicated in the Battery Charging Support Register:
0 = Battery charging not supported
1 = Battery charging supported
PWRCTL3/BATEN3 1 I/O PD USB port 3 power-on control for downstream power and battery charging enable. The pin is used for control of the downstream power switch for port 3.
The value of the pin is sampled at the deassertion of reset to determine the value of the battery charging support for Port 3 as indicated in the Battery Charging Support Register:
0 = Battery charging not supported
1 = Battery charging supported
PWRCTL4/BATEN4 64 I/O PD USB port 4 power-on control for downstream power and battery charging enable. The pin is used for control of the downstream power switch for port 4.
The value of the pin is sampled at the deassertion of reset to determine the value of the battery charging support for Port 4 as indicated in the Battery Charging Support Register:
0 = Battery charging not supported
1 = Battery charging supported
USB_DM_DN1 34 I/O — USB high-speed differential transceiver (negative)
USB_DM_DN2 42
USB_DM_DN3 50
USB_DM_DN4 57
USB_DP_DN1 33 I/O — USB high-speed differential transceiver (positive)
USB_DP_DN2 41
USB_DP_DN3 49
USB_DP_DN4 56
I2C AND SMBus SIGNALS
SCL/SMBCLK 6 I/O PD I2C clock/SMBus clock. The function of this pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin functions as the serial clock interface for an I2C EEPROM.
When SMBUSz = 0, this pin functions as the serial clock interface for an SMBus host.
This pin can be left unconnected if external interface not implemented.
SDA/SMBDAT 5 I/O PD I2C data/SMBus data. The function of this pin depends on the setting of the SMBUSz input.
When SMBUSz = 1, this pin functions as the serial data interface for an I2C EEPROM.
When SMBUSz = 0, this pin functions as the serial data interface for an SMBus host.
This pin can be left unconnected if the external interface is not implemented.
SMBUSz 7 I/O PU I2C/SMBus mode select. The value of the pin is sampled at the deassertion of reset set I2C or SMBus mode as follows:
1 = I2C mode selected
0 = SMBus mode selected
This pin can be left unconnected if the external interface is not implemented.
After reset, this signal is driven low by the TUSB4041I. Because of this behavior, TI recommends not to tie directly to supply, but instead pull up or pull down using external resistor.
TEST AND MISCELLANEOUS SIGNALS
AUTOENz/
HS_SUSPEND		 13 I/O PU Automatic charge mode enable/HS suspend status
The value of the pin is sampled at the deassertion of reset to determine if automatic mode is enabled as follows:
0 = Automatic mode is enabled on ports that are enabled for battery charging when the hub is unconnected. Note that CDP is not supported on port 1 when operating in automatic mode.
1 = Automatic mode is disabled.
This value is also used to set the autoEnz bit in the Battery Charging Support Register.
After reset, this signal indicates the high-speed USB Suspend status of the upstream port if enabled through the Additional Feature Configuration Register. When enabled, a value of 1 indicates the connection is suspended.
FULLPWRMGMTz/
SMBA1		 8 I/O PD Full power management enable/SMBus address bit 1
The value of the pin is sampled at the deassertion of reset to set the power switch control follows:
0 = Power switching and overcurrent inputs supported
1 = Power switching and overcurrent inputs not supported
Full power management is the ability to control power to the downstream ports of the TUSB4041I device using PWRCTL[4:1]/BATEN[4:1].
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 1.
This pin can be left unconnected if full power management and SMBus are not implemented.
After reset, this signal is driven low by the TUSB4041I. Because of this behavior, TI recommends not to tie directly to supply, but instead pull up or pull down using an external resistor.
Note: Power switching must be supported for battery charging applications.
GANGED/SMBA2/
HS_UP		 10 I/O PD Ganged operation enable/SMBus address bit 2/HS connection status upstream port
The value of the pin is sampled at the deassertion of reset to set the power switch and overcurrent detection mode as follows:
0 = Individual power control supported when power switching is enabled
1 = Power control gangs supported when power switching is enabled
When SMBus mode is enabled using SMBUSz, this pin sets the value of the SMBus slave address bit 2.
After reset, this signal indicates the high-speed USB connection status of the upstream port if enabled through the Additional Feature Configuration Register. When enabled, a value of 1 indicates the upstream port is connected to a high-speed USB capable port.
Note: Individual power control must be enabled for battery charging applications.
PWRCTL_POL 9 I/O PU Power control polarity.
The value of the pin is sampled at the deassertion of reset to set the polarity of PWRCTL[4:1].
0 = PWRCTL polarity is active low
1 = PWRCTL polarity is active high
RSVD 23, 24, 26, 27, 35, 36, 38, 39, 43, 44, 46, 47, 51, 52, 54, 55, 58, 59, 61, 62 I/O Reserved. For internal use only and leave unconnected on the PCB.
TEST 17 I PD This pin is reserved for factory test.
POWER AND GROUND SIGNALS
NC 28 — — No connection, leave floating
40
VDD 19 — PWR 1.1-V power rail
25
37
45
53
60
63
VDD33 2 — PWR 3.3-V power rail
20
31
48
Thermal Pad — — Ground. The thermal pad must be connected to ground.
(1) I = Input, O = Output, I/O = Input/output, PU = Internal pullup resistor, PD = Internal pulldown resistor, and PWR = Power signal