SLLSEQ5A September   2016  – December 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pull-down
      3. 9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
      4. 9.3.4 Soft Turn-Off, Fault (FLT) and Reset (RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5452-Q1 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 PCB Material
    3. 12.3 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9 Detailed Description

9.1 Overview

The ISO5452-Q1 device is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage are separated by a Silicon dioxide (SiO2) capacitive isolation.

The IO circuitry on the input side interfaces with a microcontroller and consists of gate-drive control and RESET (RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short-circuit events. The capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5452-Q1 device also has undervoltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The ISO5452-Q1 device also has an active Miller clamp function which can be used to prevent parasitic turnon of the external power transistor, because of Miller effect, for unipolar supply operation.

9.2 Functional Block Diagram

ISO5452-Q1 FBD_SLLSEQ0.gif

9.3 Feature Description

9.3.1 Supply and Active Miller Clamp

The ISO5452-Q1 device supports both bipolar and unipolar power supply with active Miller clamp.

For operation with bipolar supplies, the IGBT is turned off with a negative voltage on the gate with respect to the emitter. This prevents the IGBT from unintentionally turning on because of current induced from the collector to the gate because Miller effect. In this condition connecting the CLAMP output of the gate driver to the IGBT gate is not necessary, but connecting the CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values of VCC2 and VEE2 for bipolar operation are 15 V and –8 V with respect to GND2.

For operation with unipolar supply, typically, VCC2 is connected to 15 V with respect to GND2, and VEE2 is connected to GND2. In this use case, the IGBT can turn on because of additional charge from IGBT Miller capacitance caused by a high-voltage slew-rate transition on the IGBT collector. To prevent IGBT from turning on, the CLAMP pin is connected to IGBT gate and Miller current is sinked through a low-impedance CLAMP transistor.

Miller CLAMP is designed for miller current up to 2 A. When the IGBT is turned off and the gate voltage transitions below 2 V and the CLAMP current output is activated.

9.3.2 Active Output Pull-down

The active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to VEE2 to ensure safe IGBT off-state, when the output side is not connected to the power supply.

9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output

Undervoltage lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned off, if the supply VCC1 drops below VIT-(UVLO1), irrespective of IN+, IN– and RST input until VCC1 goes above VIT+(UVLO1).

In similar manner, the IGBT is turned off if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN– and RST input till VCC2 goes above VIT+(UVLO2).

The RDY pin indicates status of input and output side UVLO internal protection feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise, RDY pin output is high. The RDY pin also serves as an indication to the micro-controller that the device is ready for operation.

9.3.4 Soft Turn-Off, Fault (FLT) and Reset (RST)

During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables OUTH and pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a low-active pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for at least the specified minimum duration (800ns), device input logic can be enabled or disabled.

9.3.5 Short Circuit Clamp

Under short-circuit events currents can be induced back into the gate-driver OUTH/L and CLAMP pins because of parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher than the output side supply.

9.4 Device Functional Modes

For OUTH/L of the ISO5452-Q1 device to follow IN+ in normal functional mode, the RST and RDY pins must be in the high state. Table 1 lists the device functional modes

Table 1. Function Table(1)

VCC1 VCC2 IN+ IN– RST RDY OUTH/L
PU PD X X X Low Low
PD PU X X X Low Low
PU PU X X Low High Low
PU Open X X X Low Low
PU PU Low X X High Low
PU PU X High X High Low
PU PU High Low High High High
(1) PU: Power Up (VCC1 ≥ 2.25-V, VCC2 ≥ 13-V), PD: Power Down (VCC1 ≤ 1.7-V, VCC2 ≤ 9.5-V), X: Irrelevant